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* Add X86 RORX instructionCraig Topper2011-10-231-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-041-1/+4
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
* - Handle special scalar_to_vector case: splats. Using a native 128-bitBruno Cardoso Lopes2011-07-251-0/+3
| | | | | | | | | | shuffle before inserting on a 256-bit vector. - Add AVX versions of movd/movq instructions - Introduce a few COPY patterns to match insert_subvector instructions. This turns a trivial insert_subvector instruction into a register copy, coalescing the xmm into a ymm and avoid emiting on more instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136002 91177308-0d34-0410-b5e6-96231b3b80d8
* Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, ↵Eli Friedman2011-07-051-0/+5
| | | | | | use proper aliases for the pclmullqlqdq and friends. PR10269. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand Op0Mask by one bit in preparation for the PadLock prefixes.Joerg Sonnenberger2011-04-041-30/+30
| | | | | | | | | Define most shift masks incrementally to reduce the redundant hard-coding. Introduce new shift for the VEX flags to replace the magic constant 32 in various places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
* Enabled disassembler support for AVX instructionsSean Callanan2011-03-151-2/+2
| | | | | | | | | in the instruction tables and fixed a few bugs that were causing decode conflicts. Rudimentary tests are coming up in the next patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127646 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement xgetbv and xsetbv.Rafael Espindola2011-02-221-0/+2
| | | | | | Patch by Jai Menon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some grammar in comments I noticed.Eric Christopher2010-11-301-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120416 91177308-0d34-0410-b5e6-96231b3b80d8
* This defaults to GenericDomain.Eric Christopher2010-11-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120415 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement a PseudoI class and transfer the sse instructions over to useEric Christopher2010-11-301-0/+5
| | | | | | | it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120412 91177308-0d34-0410-b5e6-96231b3b80d8
* fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner2010-10-311-0/+3
| | | | | | | | | Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement support for the bizarre 3DNow! encoding (which is unlike anythingChris Lattner2010-10-031-0/+3
| | | | | | | | | | | | | else in X86), and add support for pavgusb. This is apparently the only instruction (other than movsx) that is preventing ffmpeg from building with clang. If someone else is interested in banging out the rest of the 3DNow! instructions, it should be quite easy now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8444631 - encoder crash on 'enter'Chris Lattner2010-09-171-1/+2
| | | | | | | What a weird instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment typos.Bob Wilson2010-08-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112202 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR7465, mishandling of lcall and ljmp: intersegment long Chris Lattner2010-08-191-0/+1
| | | | | | | call and jumps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
* minor progress towards fixing PR7465Chris Lattner2010-08-191-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111494 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX version of CLMUL instructionsBruno Cardoso Lopes2010-07-231-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109248 91177308-0d34-0410-b5e6-96231b3b80d8
* Add complete assembler support for FMA3 instructions, with descriptions and ↵Bruno Cardoso Lopes2010-07-231-0/+6
| | | | | | encodings taken from the AVX manual git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new AVX instruction vinsertf128Bruno Cardoso Lopes2010-07-201-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108892 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX vbroadcast new instructionBruno Cardoso Lopes2010-07-201-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108788 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX 256-bit conversion instructionsBruno Cardoso Lopes2010-07-131-0/+3
| | | | | | | Add the x86 VEX_L form to handle special cases where VEX_L must be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
* Since AVX is a superset of all SSE versions, only use HasAVX for AVX ↵Bruno Cardoso Lopes2010-07-131-12/+8
| | | | | | instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108222 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-071-3/+11
| | | | | | | | | in the integrated assembler. Still some discussion to be done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX vblendvpd, vblendvps and vpblendvb instructionsBruno Cardoso Lopes2010-07-061-0/+4
| | | | | | | Update VEX encoding to support those new instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add AVX SSE2 Move doubleword and quadword instructions.Bruno Cardoso Lopes2010-07-011-3/+6
| | | | | | | | | | - Add encode bits for VEX_W - All 128-bit SSE 1 & SSE2 instructions that are described in the .td file now have a AVX encoded form already working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r106896:Bruno Cardoso Lopes2010-06-251-4/+4
| | | | | | | | | Add several AVX MOV flavors Support VEX encoding for MRMDestReg git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcasesBruno Cardoso Lopes2010-06-241-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX compare packed instructionsBruno Cardoso Lopes2010-06-221-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX MOV{SS,SD}{rr,rm} instructionsBruno Cardoso Lopes2010-06-221-7/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo, SSE1 should be used by XS, not SSE2Bruno Cardoso Lopes2010-06-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106357 91177308-0d34-0410-b5e6-96231b3b80d8
* Apply some refactor to packed instructionsBruno Cardoso Lopes2010-06-181-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106349 91177308-0d34-0410-b5e6-96231b3b80d8
* Use new tablegen resources in SSE tablegen code. This willBruno Cardoso Lopes2010-06-171-0/+11
| | | | | | | | be done incrementally and intermixed with the adding of more AVX instructions. This is a first step in that direction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106251 91177308-0d34-0410-b5e6-96231b3b80d8
* More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rrBruno Cardoso Lopes2010-06-121-0/+10
| | | | | | | | Handle OpSize TSFlag for AVX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105869 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-0/+13
| | | | | | | immediates to avoid breaking the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-13/+0
| | | | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-0/+13
| | | | | | | yet, only assembly encoding support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove FIXME.Eric Christopher2010-04-051-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100466 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-0/+13
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate out the AES-NI instructions from the SSE4.2 instructions. AddEric Christopher2010-04-021-0/+15
| | | | | | | | | | a new subtarget option for AES and check for the support. Add "westmere" line of processors and add AES-NI support to the core i7. Add a couple of TODOs for information I couldn't verify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
* Renumber SSE execution domains for better code size.Jakob Stoklund Olesen2010-03-301-4/+4
| | | | | | | | SSEDomainFix will collapse to the domain with the lower number when it has a choice. The SSEPackedSingle domain often has smaller instructions, so prefer that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99952 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach TableGen to understand X.Y notation in the TSFlagsFields strings.Jakob Stoklund Olesen2010-03-251-6/+3
| | | | | | | Remove much horribleness from X86InstrFormats as a result. Similar simplifications are probably possible for other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain ↵Jakob Stoklund Olesen2010-03-251-19/+45
| | | | | | | | | | | | | | | | | | | | | | crossings. On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it doesKevin Enderby2010-03-241-1/+1
| | | | | | | | | not get an "Unknown immediate size" assert failure when used. All instructions of this form have an 8-bit immediate. Also added a test case of an example instruction that is of this form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
* Added the rdtscp instruction to the x86 instructionSean Callanan2010-02-131-1/+1
| | | | | | | tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96073 91177308-0d34-0410-b5e6-96231b3b80d8
* remove special cases for vmlaunch, vmresume, vmxoff, and swapgsChris Lattner2010-02-131-4/+8
| | | | | | | fix swapgs to be spelled right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
* enhance the immediate field encoding to know whether the immediateChris Lattner2010-02-121-5/+20
| | | | | | | is pc relative or not, mark call and branches as pcrel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96026 91177308-0d34-0410-b5e6-96231b3b80d8
* add a bunch of mod/rm encoding types for fixed mod/rm bytes.Chris Lattner2010-02-121-0/+5
| | | | | | | | This will work better for the disassembler for modeling things like lfence/monitor/vmcall etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95960 91177308-0d34-0410-b5e6-96231b3b80d8
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