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path: root/lib/Target/X86/X86InstrInfo.cpp
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* X86: remove redundant cmp against zero.Manman Ren2012-07-181-14/+83
* Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem2012-07-161-0/+7
* Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.Nadav Rotem2012-07-151-0/+5
* Make helper functions static.Benjamin Kramer2012-07-131-1/+1
* X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren2012-07-111-1/+22
* X86: implement functions to analyze & synthesize CMOV|SET|JccManman Ren2012-07-091-138/+185
* X86: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-071-5/+25
* X86: peephole optimization to remove cmp instructionManman Ren2012-07-061-0/+285
* Add early if-conversion support to X86.Jakob Stoklund Olesen2012-07-041-0/+80
* Remove codegen only instruction in favor of one that has the same definition....Craig Topper2012-06-251-1/+1
* Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patte...Craig Topper2012-06-241-2/+0
* Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patte...Craig Topper2012-06-241-2/+0
* Fix build failures from r159106.Craig Topper2012-06-241-2/+0
* Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns.Craig Topper2012-06-241-2/+0
* Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead ins...Craig Topper2012-06-231-2/+0
* Compress flags in X86 op folding to reduce space in static tables.Craig Topper2012-06-231-16/+16
* Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with ...Craig Topper2012-06-231-2/+0
* Move AVX version of convert instructions that write to GPRs to the Op1 table.Craig Topper2012-06-151-9/+13
* Move X86::VCVTTSD2SIrr from the 2 operand to 1 operand MemRegOp table.Pete Cooper2012-06-141-1/+1
* Revert r157755.Manman Ren2012-06-061-38/+0
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-061-3/+0
* Add intrinsic forms for FMA instructions to opcode folding tables.Craig Topper2012-06-041-105/+137
* Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 ...Craig Topper2012-06-041-0/+34
* Revert r157831Manman Ren2012-06-031-323/+0
* X86: peephole optimization to remove cmp instructionManman Ren2012-06-011-0/+323
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-011-0/+118
* Add VFNSUB* instructions to folding table.Craig Topper2012-06-011-0/+17
* X86: replace SUB with CMP if possibleManman Ren2012-05-311-0/+38
* Added FMA3 Intel instructions.Elena Demikhovsky2012-05-311-0/+70
* Make the global base reg GR32_NOSP.Jakob Stoklund Olesen2012-05-201-1/+1
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-6/+6
* Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change s...Craig Topper2012-04-201-10/+12
* Added VPERM optimization for AVX2 shufflesElena Demikhovsky2012-04-151-2/+2
* Reorder includes in Target backends to following coding standards. Remove som...Craig Topper2012-03-171-1/+1
* Use uint16_t to store opcodes in static tables in X86 backend.Craig Topper2012-03-091-21/+27
* Make all pointers to TargetRegisterClass const since they are all pointers to...Craig Topper2012-02-221-1/+1
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Use the same CALL instructions for Windows as for everything else.Jakob Stoklund Olesen2012-02-161-1/+0
* Handle register masks when searching for EFLAGS clobbers.Jakob Stoklund Olesen2012-02-091-0/+6
* Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specif...Craig Topper2012-01-251-12/+12
* Custom lower phadd and phsub intrinsics to target specific nodes. Remove the ...Craig Topper2012-01-251-12/+12
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-5/+2
* Folding table additions and fixes for AVX.Craig Topper2012-01-191-9/+21
* Add a bunch of AVX instructions to the folding tables. Also fixed the alignme...Craig Topper2012-01-141-69/+139
* Convert SHUFPD with the same register for both sources to PSHUFD if it would ...Craig Topper2012-01-131-0/+18
* Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones...Craig Topper2012-01-131-1/+3
* Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes P...Craig Topper2012-01-131-0/+2
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-2/+2
* X86: Split (v)rounds[sd] into a normal and an intrinsic version.Benjamin Kramer2011-12-091-0/+4
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-5/+4
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