| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added RCL and RCR (rotate left and right with a | Sean Callanan | 2009-09-18 | 1 | -0/+91 |
| * | Added the LODS (load byte into register, usually | Sean Callanan | 2009-09-16 | 1 | -0/+6 |
| * | Added the LAR (load segment access rights) | Sean Callanan | 2009-09-16 | 1 | -0/+13 |
| * | Added the LOOP family of instructions to the Intel | Sean Callanan | 2009-09-16 | 1 | -0/+6 |
| * | Added an alternate form of register-register CMP | Sean Callanan | 2009-09-16 | 1 | -0/+6 |
| * | Added the ENTER instruction, which sets up a stack | Sean Callanan | 2009-09-16 | 1 | -0/+5 |
| * | Added the definitions for one-bit left shifts to | Sean Callanan | 2009-09-16 | 1 | -2/+11 |
| * | Added far return instructions (that is, returns to | Sean Callanan | 2009-09-15 | 1 | -0/+4 |
| * | Updated comments per Eli's suggestion. | Sean Callanan | 2009-09-15 | 1 | -1/+2 |
| * | Added register-to-register ADD instructions to the | Sean Callanan | 2009-09-15 | 1 | -0/+8 |
| * | Added a new register class for segment registers | Sean Callanan | 2009-09-15 | 1 | -0/+10 |
| * | Modified the Intel instruction tables to include | Sean Callanan | 2009-09-15 | 1 | -4/+19 |
| * | Added the WAIT instruction to the Intel tables, | Sean Callanan | 2009-09-12 | 1 | -0/+1 |
| * | Added CMPS (string comparison) instructions for all | Sean Callanan | 2009-09-12 | 1 | -0/+4 |
| * | Added SCAS instructions in their 8, 16, 32, and | Sean Callanan | 2009-09-12 | 1 | -0/+4 |
| * | Added ADC, SUB, SBB, and OR instructions that operate | Sean Callanan | 2009-09-11 | 1 | -0/+28 |
| * | Added XOR instructions for rAX and immediates of | Sean Callanan | 2009-09-10 | 1 | -0/+7 |
| * | Added MOV instructions between rAX and memory offsets, | Sean Callanan | 2009-09-10 | 1 | -0/+14 |
| * | Added a variety of PUSH and POP instructions, including | Sean Callanan | 2009-09-10 | 1 | -3/+21 |
| * | Add a -disable-16bit flag and associated support for experimenting with | Dan Gohman | 2009-09-03 | 1 | -1/+13 |
| * | Added opaque 32-, 48-, and 80-bit memory operand types to the X86 | Sean Callanan | 2009-09-03 | 1 | -0/+13 |
| * | Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. | Sean Callanan | 2009-09-02 | 1 | -3/+18 |
| * | Added TEST %rAX, $imm instructions to the Intel tables. These are required f... | Sean Callanan | 2009-09-01 | 1 | -0/+7 |
| * | CMOV_GR8 clobbers EFLAGS when its expansion involves an xor to set | Dan Gohman | 2009-08-29 | 1 | -2/+4 |
| * | Don't mark CMOV_GR8 as two-address, or commutable, since it's a pseudo. | Dan Gohman | 2009-08-27 | 1 | -2/+2 |
| * | X86: Mark EH_RETURN as code-gen-only. | Daniel Dunbar | 2009-08-27 | 1 | -1/+1 |
| * | Expand i8 selects into control flow instead of 16-bit conditional | Dan Gohman | 2009-08-27 | 1 | -0/+12 |
| * | Don't use INSERT_SUBREG to model anyext operations on x86-64, as it | Dan Gohman | 2009-08-26 | 1 | -11/+11 |
| * | On x86-64, for a varargs function, don't store the xmm registers to | Dan Gohman | 2009-08-15 | 1 | -0/+21 |
| * | X86/AsmParser: Mark MOV64GSrm, MOV64FSrm, GS_MOV32rm, FS_MOV32rm as codegen o... | Daniel Dunbar | 2009-08-11 | 1 | -2/+2 |
| * | Add 'isCodeGenOnly' bit to Instruction .td records. | Daniel Dunbar | 2009-08-11 | 1 | -1/+2 |
| * | Added ADD instructions with rAX as one parameter to the Intel instruction | Sean Callanan | 2009-08-11 | 1 | -0/+8 |
| * | move some 32-bit instrs to x86instrinfo.td | Chris Lattner | 2009-08-11 | 1 | -0/+11 |
| * | Added the x86 INT instructions; both the special-case INT 3 and the general-case | Sean Callanan | 2009-08-11 | 1 | -0/+4 |
| * | llvm-mc/AsmMatcher: Fix thinko, Mem isn't a subclass of Imm. | Daniel Dunbar | 2009-08-10 | 1 | -1/+1 |
| * | llvm-mc/AsmMatcher: Change assembler parser match classes to their own record | Daniel Dunbar | 2009-08-10 | 1 | -7/+14 |
| * | llvm-mc/AsmParser: Implement user defined super classes. | Daniel Dunbar | 2009-08-09 | 1 | -2/+8 |
| * | llvm-mc/AsmParser: Define match classes in the .td file. | Daniel Dunbar | 2009-08-09 | 1 | -0/+3 |
| * | We need to sext global addresses in kernel code model, not zext | Anton Korobeynikov | 2009-08-06 | 1 | -3/+5 |
| * | Missed part of recent kernel codemodel tweaks | Anton Korobeynikov | 2009-08-06 | 1 | -2/+4 |
| * | Enable the new no-SP register classes by default. This is to address | Dan Gohman | 2009-08-05 | 1 | -1/+1 |
| * | Major calling convention code refactoring. | Dan Gohman | 2009-08-05 | 1 | -15/+0 |
| * | Unbreak Win64 CC. Step one: honour register save area, fix some alignment and... | Anton Korobeynikov | 2009-08-03 | 1 | -0/+2 |
| * | Add a comment. | Dan Gohman | 2009-08-02 | 1 | -0/+1 |
| * | Resync lea32addr and lea64addr. | Dan Gohman | 2009-08-02 | 1 | -1/+2 |
| * | Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch(... | Evan Cheng | 2009-07-30 | 1 | -0/+72 |
| * | Add a new register class to describe operands that can't be SP, | Dan Gohman | 2009-07-30 | 1 | -2/+5 |
| * | Added a 2+-byte NOP instruction to the Intel tables, | Sean Callanan | 2009-07-23 | 1 | -1/+4 |
| * | Added the unconditional JMP with an 8-bit relocation for the | Sean Callanan | 2009-07-22 | 1 | -1/+3 |
| * | Add jumps with 8-bit relocation for assembler / disassembler. Patch by Sean C... | Evan Cheng | 2009-07-21 | 1 | -0/+24 |
