| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | One more round of reorg so sabre doesn't freak out. :-) | Evan Cheng | 2006-02-21 | 1 | -75/+19 |
| * | A big more cleaning up. | Evan Cheng | 2006-02-21 | 1 | -19/+18 |
| * | Moving things to their proper places. | Evan Cheng | 2006-02-21 | 1 | -202/+0 |
| * | Split instruction info into multiple files, one for each of x87, MMX, and SSE. | Evan Cheng | 2006-02-21 | 1 | -590/+4 |
| * | Added separate alias instructions for SSE logical ops that operate on non-pac... | Evan Cheng | 2006-02-21 | 1 | -96/+171 |
| * | Added MMX and XMM packed integer move instructions, movd and movq. | Evan Cheng | 2006-02-21 | 1 | -0/+46 |
| * | Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit | Evan Cheng | 2006-02-20 | 1 | -8/+8 |
| * | Added fisttp for fp to int conversion. | Evan Cheng | 2006-02-18 | 1 | -0/+15 |
| * | x86 / Darwin PIC support. | Evan Cheng | 2006-02-18 | 1 | -0/+7 |
| * | kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC | Nate Begeman | 2006-02-17 | 1 | -37/+28 |
| * | pxor (for FLD0SS) encoding was missing the OpSize prefix. | Evan Cheng | 2006-02-16 | 1 | -1/+1 |
| * | 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This | Evan Cheng | 2006-02-16 | 1 | -11/+20 |
| * | MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg. | Evan Cheng | 2006-02-16 | 1 | -2/+2 |
| * | cvtsd2ss / cvtss2sd encoding bug. | Evan Cheng | 2006-02-15 | 1 | -4/+4 |
| * | movaps, movapd encoding bug. | Evan Cheng | 2006-02-15 | 1 | -8/+8 |
| * | Eliminate the printCallOperand method, using a 'call' modifier on | Chris Lattner | 2006-02-06 | 1 | -6/+2 |
| * | Remove an unnecessary predicate. | Evan Cheng | 2006-02-04 | 1 | -2/+1 |
| * | Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a | Evan Cheng | 2006-02-04 | 1 | -1/+4 |
| * | Rearrange code to my liking. :) | Evan Cheng | 2006-02-01 | 1 | -50/+51 |
| * | - Use xor to clear integer registers (set R, 0). | Evan Cheng | 2006-02-01 | 1 | -5/+18 |
| * | - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. | Evan Cheng | 2006-01-31 | 1 | -15/+67 |
| * | * Fix 80-column violations | Chris Lattner | 2006-01-31 | 1 | -1/+1 |
| * | Added custom lowering of fabs | Evan Cheng | 2006-01-31 | 1 | -2/+34 |
| * | Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 | Evan Cheng | 2006-01-30 | 1 | -2/+5 |
| * | The FP stack doesn't support UNDEF, ask the legalizer to legalize it | Chris Lattner | 2006-01-29 | 1 | -4/+0 |
| * | AT&T assembly convention: registers are in lower case. | Evan Cheng | 2006-01-27 | 1 | -16/+16 |
| * | x86 CPU detection and proper subtarget support | Evan Cheng | 2006-01-27 | 1 | -4/+4 |
| * | PHI and INLINEASM are now built-in instructions provided by Target.td | Chris Lattner | 2006-01-27 | 1 | -3/+0 |
| * | Remove the uses of STATUS flag register. Rely on node property SDNPInFlag, | Evan Cheng | 2006-01-26 | 1 | -251/+221 |
| * | Emit the copies out of call return registers *after* the ISD::CALLSEQ_END | Chris Lattner | 2006-01-24 | 1 | -1/+1 |
| * | Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual). | Evan Cheng | 2006-01-21 | 1 | -6/+6 |
| * | A few more SH{L|R}D peepholes. | Evan Cheng | 2006-01-20 | 1 | -0/+16 |
| * | Added i16 SH{L|R}D patterns. | Evan Cheng | 2006-01-19 | 1 | -2/+12 |
| * | adc and sbb need an incoming flag to ensure it reads the carry flag | Evan Cheng | 2006-01-19 | 1 | -2/+3 |
| * | Two peepholes: | Evan Cheng | 2006-01-19 | 1 | -0/+10 |
| * | Zero extending load from i1 to i8. | Evan Cheng | 2006-01-17 | 1 | -0/+2 |
| * | Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should | Evan Cheng | 2006-01-17 | 1 | -2/+2 |
| * | More typo's | Evan Cheng | 2006-01-16 | 1 | -2/+2 |
| * | Some typo's | Evan Cheng | 2006-01-16 | 1 | -13/+12 |
| * | Fix FP_TO_INT**_IN_MEM lowering. | Evan Cheng | 2006-01-16 | 1 | -2/+25 |
| * | Added patterns for 8-bit multiply | Evan Cheng | 2006-01-15 | 1 | -2/+11 |
| * | bswap implementation | Nate Begeman | 2006-01-14 | 1 | -1/+3 |
| * | A typo. | Evan Cheng | 2006-01-14 | 1 | -1/+1 |
| * | Add truncstore i1 patterns. | Evan Cheng | 2006-01-13 | 1 | -0/+5 |
| * | Fix sint_to_fp (fild*) support. | Evan Cheng | 2006-01-12 | 1 | -17/+18 |
| * | Specify transformation from GlobalAddress to TargetGlobalAddress and | Evan Cheng | 2006-01-12 | 1 | -2/+2 |
| * | X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be | Evan Cheng | 2006-01-12 | 1 | -1/+2 |
| * | * Materialize GlobalAddress and ExternalSym with MOV32ri rather than | Evan Cheng | 2006-01-12 | 1 | -2/+5 |
| * | Added ROTL and ROTR. | Evan Cheng | 2006-01-11 | 1 | -24/+56 |
| * | Support for MEMCPY and MEMSET. | Evan Cheng | 2006-01-11 | 1 | -6/+19 |
