| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | - Use a different wrapper node for RIP-relative GV, etc. | Evan Cheng | 2006-11-30 | 1 | -1/+4 |
| * | Custom lower READCYCLECOUNTER for x86-64. | Evan Cheng | 2006-11-29 | 1 | -6/+2 |
| * | remove dead/redundant vars | Chris Lattner | 2006-11-03 | 1 | -2/+0 |
| * | Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4 | Reid Spencer | 2006-10-30 | 1 | -3/+3 |
| * | Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. | Evan Cheng | 2006-10-13 | 1 | -2/+2 |
| * | Move the Imp tblgen class from the X86 backend to common code. | Chris Lattner | 2006-10-12 | 1 | -5/+0 |
| * | Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice | Chris Lattner | 2006-10-12 | 1 | -2/+6 |
| * | Add properties to ComplexPattern. | Evan Cheng | 2006-10-11 | 1 | -2/+2 |
| * | Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. | Evan Cheng | 2006-10-09 | 1 | -19/+19 |
| * | Delete dead code; fix 80 col violations. | Evan Cheng | 2006-09-22 | 1 | -11/+4 |
| * | X86ISD::CMP now produces a chain as well as a flag. Make that the chain | Evan Cheng | 2006-09-11 | 1 | -11/+9 |
| * | Committing X86-64 support. | Evan Cheng | 2006-09-08 | 1 | -38/+56 |
| * | Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns | Chris Lattner | 2006-09-07 | 1 | -24/+26 |
| * | Consistency. | Evan Cheng | 2006-09-07 | 1 | -1/+1 |
| * | CALLSEQ_* produces chain even if that's not needed. | Evan Cheng | 2006-08-11 | 1 | -1/+1 |
| * | Clean up. | Evan Cheng | 2006-07-20 | 1 | -3/+3 |
| * | INC / DEC instructions have shorter code size than ADD32ri8, etc. | Evan Cheng | 2006-07-19 | 1 | -4/+12 |
| * | Emit inc / dec of registers as one byte instruction. | Evan Cheng | 2006-07-11 | 1 | -4/+4 |
| * | Add shift and rotate by 1 instructions / patterns. | Evan Cheng | 2006-06-29 | 1 | -0/+113 |
| * | Remove dead code. | Evan Cheng | 2006-06-27 | 1 | -6/+0 |
| * | X86 call instructions can take variable number of operands. Parameters of | Evan Cheng | 2006-06-14 | 1 | -5/+6 |
| * | Incorrect AT&T opcode. | Evan Cheng | 2006-06-02 | 1 | -1/+1 |
| * | Rename ASM modifier trunc8, trunc16 to subreg8, subreg16. | Evan Cheng | 2006-05-31 | 1 | -3/+3 |
| * | Sign extender | Evan Cheng | 2006-05-31 | 1 | -8/+10 |
| * | A addressing mode folding enhancement: | Evan Cheng | 2006-05-30 | 1 | -1/+1 |
| * | Remove unused patterns. | Evan Cheng | 2006-05-20 | 1 | -6/+2 |
| * | - Use exact-width integer types, e.g. int32_t, to avoid confusion. | Evan Cheng | 2006-05-19 | 1 | -8/+9 |
| * | Explicitly specify MOV32mi can only be used store 32-bit GV, etc. | Evan Cheng | 2006-05-19 | 1 | -2/+2 |
| * | Use generic iPTR instead i32 to represent pointer type. | Evan Cheng | 2006-05-17 | 1 | -3/+3 |
| * | X86 integer register classes naming changes. Make them consistent with FP, ve... | Evan Cheng | 2006-05-16 | 1 | -744/+744 |
| * | Fixing truncate. Previously we were emitting truncate from r16 to r8 as | Evan Cheng | 2006-05-08 | 1 | -7/+25 |
| * | Need extload patterns after Chris' DAG combiner changes | Evan Cheng | 2006-05-05 | 1 | -1/+11 |
| * | Better implementation of truncate. ISel matches it to a pseudo instruction | Evan Cheng | 2006-05-05 | 1 | -0/+11 |
| * | Make x86 isel lowering produce tailcall nodes. They are match to normal calls | Evan Cheng | 2006-04-27 | 1 | -0/+16 |
| * | Optimized stores to the constant pool, while cool, are unnecessary. | Nate Begeman | 2006-04-22 | 1 | -3/+0 |
| * | JumpTable support! What this represents is working asm and jit support for | Nate Begeman | 2006-04-22 | 1 | -1/+13 |
| * | - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. | Evan Cheng | 2006-04-03 | 1 | -0/+1 |
| * | Added missing (any_extend (load ...)) patterns. | Evan Cheng | 2006-03-25 | 1 | -0/+3 |
| * | Fix the encodings of these new instructions, hopefully fixing the JIT | Chris Lattner | 2006-03-23 | 1 | -4/+4 |
| * | Add support for 8 bit immediates with 16/32 bit cmp instructions | Nate Begeman | 2006-03-23 | 1 | -0/+16 |
| * | Use the generic vector register classes VR64 / VR128 rather than V4F32, | Evan Cheng | 2006-03-18 | 1 | -39/+0 |
| * | Move some pattern fragments to the right files. | Evan Cheng | 2006-03-17 | 1 | -27/+1 |
| * | - Nuke 16-bit SBB instructions. We'll never use them. | Evan Cheng | 2006-03-17 | 1 | -21/+0 |
| * | X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag. | Evan Cheng | 2006-03-07 | 1 | -2/+2 |
| * | Enable Dwarf debugging info. | Evan Cheng | 2006-03-07 | 1 | -0/+13 |
| * | remove the read/write port/io intrinsics. | Chris Lattner | 2006-03-03 | 1 | -12/+12 |
| * | * Allow mul, shl nodes to be codegen'd as LEA (if appropriate). | Evan Cheng | 2006-02-25 | 1 | -1/+24 |
| * | - Clean up the lowering and selection code of ConstantPool, GlobalAddress, | Evan Cheng | 2006-02-23 | 1 | -8/+2 |
| * | PIC related bug fixes. | Evan Cheng | 2006-02-23 | 1 | -0/+2 |
| * | Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. | Evan Cheng | 2006-02-22 | 1 | -3/+4 |
