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path: root/lib/Target/X86/X86InstrInfo.td
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* Long double patch 4 of N: initial x87 implementation.Dale Johannesen2007-08-051-0/+2
* Switch some multiplication instructions over to the new scheme for testing.Evan Cheng2007-08-021-6/+6
* Mac OS X X86-64 low 4G address not available.Evan Cheng2007-08-011-0/+1
* Be more precise.Evan Cheng2007-08-011-1/+1
* Change the x86 assembly output to use tab characters to separate theDan Gohman2007-07-311-487/+487
* Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v...Evan Cheng2007-07-311-130/+8
* Change the x86 backend to use extract_subreg for truncation operations. Passe...Christopher Lamb2007-07-291-8/+0
* In the .loc directive, print the fields as "debug" fields, so theyDan Gohman2007-07-261-1/+1
* No more noResults.Evan Cheng2007-07-211-8/+8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-526/+532
* Long live the exception handling!Anton Korobeynikov2007-07-141-0/+16
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+2
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-2/+0
* Reference correct headerNate Begeman2007-05-061-1/+1
* Add SSSE3 as a feature of Core2. Add MMX registers to the list of registersBill Wendling2007-04-251-0/+1
* X86 TLS: optimize the implementation of "local exec" model.Lauro Ramos Venancio2007-04-231-3/+10
* X86 TLS: fix and optimize the implementation of "initial exec" model.Lauro Ramos Venancio2007-04-221-1/+6
* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-201-0/+22
* Implemented correct stack probing on mingw/cygwin for dynamic alloca's.Anton Korobeynikov2007-04-171-0/+3
* Add support for our first SSSE3 instruction "pmulhrsw".Bill Wendling2007-04-101-0/+3
* Mark re-materializable instructions.Evan Cheng2007-03-211-0/+2
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-4/+0
* Fix a misencoding of CBW and CWD. This fixes PR1030.Chris Lattner2007-01-241-2/+2
* - Switch X86-64 JIT to large code size model.Evan Cheng2006-12-051-9/+10
* - Use a different wrapper node for RIP-relative GV, etc.Evan Cheng2006-11-301-1/+4
* Custom lower READCYCLECOUNTER for x86-64.Evan Cheng2006-11-291-6/+2
* remove dead/redundant varsChris Lattner2006-11-031-2/+0
* Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4Reid Spencer2006-10-301-3/+3
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-2/+2
* Move the Imp tblgen class from the X86 backend to common code.Chris Lattner2006-10-121-5/+0
* Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will noticeChris Lattner2006-10-121-2/+6
* Add properties to ComplexPattern.Evan Cheng2006-10-111-2/+2
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-19/+19
* Delete dead code; fix 80 col violations.Evan Cheng2006-09-221-11/+4
* X86ISD::CMP now produces a chain as well as a flag. Make that the chainEvan Cheng2006-09-111-11/+9
* Committing X86-64 support.Evan Cheng2006-09-081-38/+56
* Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patternsChris Lattner2006-09-071-24/+26
* Consistency.Evan Cheng2006-09-071-1/+1
* CALLSEQ_* produces chain even if that's not needed.Evan Cheng2006-08-111-1/+1
* Clean up.Evan Cheng2006-07-201-3/+3
* INC / DEC instructions have shorter code size than ADD32ri8, etc.Evan Cheng2006-07-191-4/+12
* Emit inc / dec of registers as one byte instruction.Evan Cheng2006-07-111-4/+4
* Add shift and rotate by 1 instructions / patterns.Evan Cheng2006-06-291-0/+113
* Remove dead code.Evan Cheng2006-06-271-6/+0
* X86 call instructions can take variable number of operands. Parameters ofEvan Cheng2006-06-141-5/+6
* Incorrect AT&T opcode.Evan Cheng2006-06-021-1/+1
* Rename ASM modifier trunc8, trunc16 to subreg8, subreg16.Evan Cheng2006-05-311-3/+3
* Sign extenderEvan Cheng2006-05-311-8/+10
* A addressing mode folding enhancement:Evan Cheng2006-05-301-1/+1
* Remove unused patterns.Evan Cheng2006-05-201-6/+2
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