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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-380/+452
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-18/+15
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-21/+3
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-44/+156
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-273/+575
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,Yunzhong Gao2013-10-161-1/+1
| | | | | | | | | | | bulldozer and piledriver. Support for the instruction itself seems to have already been added in r178040. Differential Revision: http://llvm-reviews.chandlerc.com/D1933 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192828 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-0/+8
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove underscores from TBM instruction names for consistency with other ↵Craig Topper2013-10-051-24/+24
| | | | | | instruction naming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192040 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns ↵Craig Topper2013-10-051-39/+20
| | | | | | are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into ↵Craig Topper2013-10-051-0/+6
| | | | | | (sub -2, x). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for selecting TBM instructions from logical operations. Patch ↵Craig Topper2013-10-031-16/+81
| | | | | | from Yunzhong Gao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
* BEXTR should be defined to take same type for bother operands.Craig Topper2013-10-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191728 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-271-0/+79
| | | | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-12/+15
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+1
| | | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
* Add neverHasSideEffects=1 on a couple move instructions.Craig Topper2013-09-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190259 91177308-0d34-0410-b5e6-96231b3b80d8
* Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). ↵Craig Topper2013-09-021-0/+10
| | | | | | Fixes PR17028. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189742 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup BZHI selection to remove an unneeded zero extension.Craig Topper2013-08-301-9/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189656 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused X86andn_flag node.Craig Topper2013-08-301-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189654 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ↵Craig Topper2013-08-301-0/+10
| | | | | | Y), -1)). Fixes PR17038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189653 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some unnecessary PredicateMethod overrides. Add RenderMethod ↵Craig Topper2013-08-261-15/+19
| | | | | | overrides to remove forwarding in the X86AsmParser code itself. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189205 91177308-0d34-0410-b5e6-96231b3b80d8
* Put some of the AVX-512 parsing stuff in a more consistent place with the ↵Craig Topper2013-08-251-7/+6
| | | | | | existing functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189204 91177308-0d34-0410-b5e6-96231b3b80d8
* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-251-11/+39
| | | | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189201 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hasSideEffects/mayLoad/mayStore flags to the X86 ↵Craig Topper2013-08-241-0/+11
| | | | | | moffs8/moffs16/moffs32/moffs64 versions of move. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189182 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing whitespace.Craig Topper2013-08-241-21/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189178 91177308-0d34-0410-b5e6-96231b3b80d8
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-311-0/+1
| | | | | | | | | | All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-54/+54
| | | | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed incorrect disassembly for MOV16o16a when using Intel syntax.Craig Topper2013-07-311-2/+2
| | | | | | | | Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187471 91177308-0d34-0410-b5e6-96231b3b80d8
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-0/+35
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix more Intel syntax issues with FP instruction aliases. Test cases coming ↵Craig Topper2013-07-261-8/+8
| | | | | | in a subsequent patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187187 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix aliases for shrd/shld to handle Intel syntax properly. Also suppress ↵Craig Topper2013-07-241-13/+13
| | | | | | them from being used by the asm printer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187020 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-231-1/+1
| | | | | | normal movsl instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r186907 to fix bots.Craig Topper2013-07-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186910 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-231-1/+1
| | | | | | normal movsl instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186907 91177308-0d34-0410-b5e6-96231b3b80d8
* Add aliases to map 'imm, mem' form of x86 bts/btr/btc without a size suffix ↵Craig Topper2013-07-231-0/+7
| | | | | | | | | to their 32-bit forms. This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186904 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicitly don't let the asm printer use the clrb/w/l aliases for xor %reg, ↵Craig Topper2013-07-231-4/+4
| | | | | | | | | | %reg. It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186900 91177308-0d34-0410-b5e6-96231b3b80d8
* Suppress argumentless aliases for some x86 FP operations from being used by ↵Craig Topper2013-07-231-14/+14
| | | | | | the asm writer. Prefer to use the explicit %st(1) form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186897 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-221-15/+27
| | | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r186813: More Intel syntax alias fixes. With the addition of ↵Craig Topper2013-07-221-28/+28
| | | | | | suppressing some of the aliases from being emitted by the asm printer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "More Intel syntax alias fixes."Tim Northover2013-07-221-28/+28
| | | | | | This reverts commit r186813, which broke the bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186818 91177308-0d34-0410-b5e6-96231b3b80d8
* More Intel syntax alias fixes.Craig Topper2013-07-221-14/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186814 91177308-0d34-0410-b5e6-96231b3b80d8
* More Intel syntax alias fixes.Craig Topper2013-07-221-28/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186813 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Intel variants to aliases for some FP instructions.Craig Topper2013-07-221-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186811 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse operands for Intel syntax form of 'bt' alias.Craig Topper2013-07-221-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186809 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: POP*rmm: move address operand to (ins) from (outs).Ahmed Bougacha2013-06-301-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185292 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Make the cmov aliases work with intel syntax too.Benjamin Kramer2013-06-131-21/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183907 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-101-3/+2
| | | | | | | | | | | | Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-011-2/+3
| | | | | | Very sorry, it was committed from the wrong branch by mistake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
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