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path: root/lib/Target/X86/X86InstrMMX.td
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* Handle a few more cases of folding load i64 into xmm and zero top bits.Evan Cheng2008-05-091-4/+4
* Handle vector move / load which zero the destination register top bits (i.e. ...Evan Cheng2008-05-081-17/+9
* Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This ...Evan Cheng2008-05-031-14/+11
* Fix illegal MMX_MOVDQ2Qrr pattern. vector_extract result must be a scalar value.Evan Cheng2008-04-251-2/+15
* Special handling for MMX values being passed in either GPR64 or lower 64-bits...Evan Cheng2008-04-251-0/+4
* Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller typ...Evan Cheng2008-04-251-2/+4
* Fix the encoding of the MMX movd that moves from MMX to 64-bit GPR.Dan Gohman2008-04-211-1/+1
* Add movd instructions to move from MMX registersDan Gohman2008-04-151-0/+12
* Undo 48570. Correctly match mmx shift instructions with an immediate operand.Evan Cheng2008-03-211-16/+24
* Add intrinsics to match mmx shift builtin's with immediate operand.Evan Cheng2008-03-191-11/+11
* Replace all target specific implicit def instructions with a target independe...Evan Cheng2008-03-151-13/+0
* Clean up my own mess.Evan Cheng2008-03-121-0/+6
* Use the correct instruction encodings for the 64-bit MMX movd.Anders Carlsson2008-02-291-2/+2
* - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should c...Evan Cheng2008-02-181-15/+14
* Start inferring side effect information more aggressively, and fix many bugs ...Chris Lattner2008-01-101-1/+14
* remove explicit sets of 'neverHasSideEffects' that can now be Chris Lattner2008-01-101-1/+1
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-2/+2
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. IBill Wendling2007-12-171-3/+3
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materia...Evan Cheng2007-12-121-0/+1
* Fix a long standing deficiency in the X86 backend: we wouldChris Lattner2007-11-251-21/+8
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-2/+2
* Mark load instructions with isLoad = 1.Evan Cheng2007-08-301-2/+2
* Mark the SSE and MMX load instructions thatDan Gohman2007-08-021-0/+2
* Change the x86 assembly output to use tab characters to separate theDan Gohman2007-07-311-56/+56
* Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v...Evan Cheng2007-07-311-23/+0
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-71/+71
* It's not necessary to do rounding for alloca operations when the requestedDan Gohman2007-07-181-0/+645
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