| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but | Bill Wendling | 2009-05-28 | 1 | -1/+1 |
| * | 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. | Nate Begeman | 2009-04-27 | 1 | -67/+47 |
| * | Revert 69952. Causes testsuite failures on linux x86-64. | Rafael Espindola | 2009-04-24 | 1 | -47/+67 |
| * | PR2957 | Nate Begeman | 2009-04-24 | 1 | -67/+47 |
| * | Only v1i16 (i.e. _m64) is returned via RAX / RDX. | Evan Cheng | 2009-02-23 | 1 | -6/+26 |
| * | Added support for SELECT v8i8 v4i16 for X86 (MMX) | Mon P Wang | 2008-12-12 | 1 | -0/+11 |
| * | Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register. | Evan Cheng | 2008-12-03 | 1 | -3/+13 |
| * | Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. | Dan Gohman | 2008-12-03 | 1 | -2/+2 |
| * | Add more vector move low and zero-extend patterns. | Evan Cheng | 2008-11-05 | 1 | -0/+9 |
| * | Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the | Bill Wendling | 2008-08-27 | 1 | -3/+3 |
| * | Nevermind. This broke the bootstrap (?!). | Bill Wendling | 2008-08-25 | 1 | -3/+3 |
| * | MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these | Bill Wendling | 2008-08-25 | 1 | -3/+3 |
| * | Provide a 64 bit variant of mmx.maskmovq intrinsic lowering. | Anton Korobeynikov | 2008-08-23 | 1 | -0/+4 |
| * | Remove dead PatLeaf; there are a number of issues around MMX movl that need t... | Nate Begeman | 2008-07-25 | 1 | -5/+0 |
| * | Add v2f32 (MMX) type to X86. Support is primitive: | Dale Johannesen | 2008-06-24 | 1 | -0/+14 |
| * | Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. | Evan Cheng | 2008-05-29 | 1 | -0/+6 |
| * | Handle a few more cases of folding load i64 into xmm and zero top bits. | Evan Cheng | 2008-05-09 | 1 | -4/+4 |
| * | Handle vector move / load which zero the destination register top bits (i.e. ... | Evan Cheng | 2008-05-08 | 1 | -17/+9 |
| * | Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This ... | Evan Cheng | 2008-05-03 | 1 | -14/+11 |
| * | Fix illegal MMX_MOVDQ2Qrr pattern. vector_extract result must be a scalar value. | Evan Cheng | 2008-04-25 | 1 | -2/+15 |
| * | Special handling for MMX values being passed in either GPR64 or lower 64-bits... | Evan Cheng | 2008-04-25 | 1 | -0/+4 |
| * | Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller typ... | Evan Cheng | 2008-04-25 | 1 | -2/+4 |
| * | Fix the encoding of the MMX movd that moves from MMX to 64-bit GPR. | Dan Gohman | 2008-04-21 | 1 | -1/+1 |
| * | Add movd instructions to move from MMX registers | Dan Gohman | 2008-04-15 | 1 | -0/+12 |
| * | Undo 48570. Correctly match mmx shift instructions with an immediate operand. | Evan Cheng | 2008-03-21 | 1 | -16/+24 |
| * | Add intrinsics to match mmx shift builtin's with immediate operand. | Evan Cheng | 2008-03-19 | 1 | -11/+11 |
| * | Replace all target specific implicit def instructions with a target independe... | Evan Cheng | 2008-03-15 | 1 | -13/+0 |
| * | Clean up my own mess. | Evan Cheng | 2008-03-12 | 1 | -0/+6 |
| * | Use the correct instruction encodings for the 64-bit MMX movd. | Anders Carlsson | 2008-02-29 | 1 | -2/+2 |
| * | - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should c... | Evan Cheng | 2008-02-18 | 1 | -15/+14 |
| * | Start inferring side effect information more aggressively, and fix many bugs ... | Chris Lattner | 2008-01-10 | 1 | -1/+14 |
| * | remove explicit sets of 'neverHasSideEffects' that can now be | Chris Lattner | 2008-01-10 | 1 | -1/+1 |
| * | rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. | Chris Lattner | 2008-01-06 | 1 | -2/+2 |
| * | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 | 1 | -2/+2 |
| * | Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I | Bill Wendling | 2007-12-17 | 1 | -3/+3 |
| * | Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materia... | Evan Cheng | 2007-12-12 | 1 | -0/+1 |
| * | Fix a long standing deficiency in the X86 backend: we would | Chris Lattner | 2007-11-25 | 1 | -21/+8 |
| * | Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. | Evan Cheng | 2007-09-11 | 1 | -2/+2 |
| * | Mark load instructions with isLoad = 1. | Evan Cheng | 2007-08-30 | 1 | -2/+2 |
| * | Mark the SSE and MMX load instructions that | Dan Gohman | 2007-08-02 | 1 | -0/+2 |
| * | Change the x86 assembly output to use tab characters to separate the | Dan Gohman | 2007-07-31 | 1 | -56/+56 |
| * | Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v... | Evan Cheng | 2007-07-31 | 1 | -23/+0 |
| * | Change instruction description to split OperandList into OutOperandList and | Evan Cheng | 2007-07-19 | 1 | -71/+71 |
| * | It's not necessary to do rounding for alloca operations when the requested | Dan Gohman | 2007-07-18 | 1 | -0/+645 |
