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path: root/lib/Target/X86/X86InstrSSE.td
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* Add missing SSE builtins: CVTPD2PI, CVTPS2PI,Dale Johannesen2007-10-301-0/+51
* Corrected many typing errors. And removed 'nest' parameter handlingArnold Schwaighofer2007-10-121-1/+1
* Add missing argument to PALIGNRDale Johannesen2007-10-111-4/+4
* Added DAG xforms. e.g.Evan Cheng2007-10-061-8/+0
* Typo. X86comi doesn't read / write chain's.Evan Cheng2007-10-011-2/+1
* Enabling new condition code modeling scheme.Evan Cheng2007-09-291-103/+29
* Added support for new condition code modeling scheme (i.e. physical register ...Evan Cheng2007-09-251-1/+98
* Fix PR 1681. When X86 target uses +sse -sse2,Dale Johannesen2007-09-231-1/+1
* Add implicit def of EFLAGS on those instructions that may modify flags.Evan Cheng2007-09-141-0/+4
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-2/+2
* Avoid storing and reloading zeros and other constants from stack slotsDan Gohman2007-09-071-0/+2
* Mark load instructions with isLoad = 1.Evan Cheng2007-08-301-4/+12
* 64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment.Bill Wendling2007-08-111-6/+21
* For kicks, I though it would be fun to use the correct opcode.Bill Wendling2007-08-101-31/+32
* Adding SSSE3 intrinsics.Bill Wendling2007-08-101-17/+284
* Fix the alignment requirements of several unpck and shuf instructions.Dan Gohman2007-08-021-10/+15
* Fix pastos in vector arithmetic intrinsics.Dan Gohman2007-08-021-4/+4
* Mark the SSE and MMX load instructions thatDan Gohman2007-08-021-0/+4
* Missing Requires.Evan Cheng2007-08-011-2/+2
* Change the x86 assembly output to use tab characters to separate theDan Gohman2007-07-311-302/+302
* Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v...Evan Cheng2007-07-311-41/+8
* Re-apply 40504, but with a fix for the segfault it caused in oggenc:Dan Gohman2007-07-271-22/+21
* Reverting 40504 for now. It's breaking oggenc.Evan Cheng2007-07-271-14/+17
* Fix a whitespace difference between CMPSSrr and CMPSDrr.Dan Gohman2007-07-261-2/+1
* Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from theDan Gohman2007-07-261-17/+14
* Because we promote SSE logical ops and loads to v2i64, we often end up generateEvan Cheng2007-07-201-11/+27
* Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG ...Evan Cheng2007-07-191-12/+12
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-337/+341
* Implement initial memory alignment awareness for SSE instructions. Vector loadsDan Gohman2007-07-181-59/+126
* It's not necessary to do rounding for alloca operations when the requestedDan Gohman2007-07-181-0/+2572
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