| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fix a duplicated pattern. | Evan Cheng | 2008-05-23 | 1 | -2/+2 |
| * | Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add | Dan Gohman | 2008-05-23 | 1 | -7/+8 |
| * | Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed man... | Evan Cheng | 2008-05-23 | 1 | -57/+79 |
| * | Add missing patterns. | Evan Cheng | 2008-05-22 | 1 | -0/+10 |
| * | movsd and movq do not require 16-byte alignment. This fixes vec_set-5.ll on L... | Evan Cheng | 2008-05-20 | 1 | -4/+10 |
| * | Fix one more encoding bug. | Nate Begeman | 2008-05-13 | 1 | -1/+1 |
| * | Fix and encoding error in the psrad xmm, imm8 instruction. | Nate Begeman | 2008-05-13 | 1 | -1/+1 |
| * | Teach Legalize how to scalarize VSETCC | Nate Begeman | 2008-05-12 | 1 | -0/+27 |
| * | Initial X86 codegen support for VSETCC. | Nate Begeman | 2008-05-12 | 1 | -10/+35 |
| * | Some clean up. | Evan Cheng | 2008-05-10 | 1 | -16/+18 |
| * | Add a pattern to do move the low element of a v4f32 and zero extend the rest. | Evan Cheng | 2008-05-09 | 1 | -0/+2 |
| * | Handle a few more cases of folding load i64 into xmm and zero top bits. | Evan Cheng | 2008-05-09 | 1 | -14/+20 |
| * | Use movq to move low half of XMM register and zero-extend the rest. | Evan Cheng | 2008-05-08 | 1 | -1/+2 |
| * | Handle vector move / load which zero the destination register top bits (i.e. ... | Evan Cheng | 2008-05-08 | 1 | -41/+23 |
| * | Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This ... | Evan Cheng | 2008-05-03 | 1 | -58/+33 |
| * | 80 column violation. | Evan Cheng | 2008-05-02 | 1 | -6/+12 |
| * | A better fix for my previous patch, MOVZQI2PQIrr just requires SSE2. | Chris Lattner | 2008-04-20 | 1 | -1/+1 |
| * | Add support for the form of the SSE41 extractps instruction that | Dan Gohman | 2008-04-16 | 1 | -3/+2 |
| * | Fix the x86-64 side of PR2108 by adding a v2f64 version of | Chris Lattner | 2008-04-10 | 1 | -0/+10 |
| * | Favors pshufd over shufps when shuffling elements from one vector. pshufd is ... | Evan Cheng | 2008-04-05 | 1 | -7/+1 |
| * | Fix some SSE4.1 instruction encoding bugs. | Evan Cheng | 2008-03-26 | 1 | -4/+4 |
| * | - SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fi... | Evan Cheng | 2008-03-24 | 1 | -5/+8 |
| * | Add a couple missing SSE4 instructions | Nate Begeman | 2008-03-16 | 1 | -0/+11 |
| * | Replace all target specific implicit def instructions with a target independe... | Evan Cheng | 2008-03-15 | 1 | -25/+0 |
| * | Fix some 80 col violations. | Evan Cheng | 2008-03-14 | 1 | -22/+22 |
| * | Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc... | Evan Cheng | 2008-03-14 | 1 | -25/+25 |
| * | Clean up my own mess. | Evan Cheng | 2008-03-12 | 1 | -0/+8 |
| * | Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ... | Evan Cheng | 2008-03-08 | 1 | -6/+9 |
| * | isTwoAddress = 1 -> Constraints. | Evan Cheng | 2008-03-05 | 1 | -47/+47 |
| * | PSLLWri etc. are two-address instructions. | Evan Cheng | 2008-03-05 | 1 | -1/+3 |
| * | - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should c... | Evan Cheng | 2008-02-18 | 1 | -33/+54 |
| * | llvm.memory.barrier, and impl for x86 and alpha | Andrew Lenharth | 2008-02-16 | 1 | -0/+8 |
| * | SSE4.1 64b integer insert/extract pattern support | Nate Begeman | 2008-02-12 | 1 | -29/+0 |
| * | Enable SSE4 codegen and pattern matching. | Nate Begeman | 2008-02-11 | 1 | -23/+111 |
| * | xmm0 variable blends | Nate Begeman | 2008-02-10 | 1 | -2/+27 |
| * | memopv16i8 had wrong alignment requirement, would have broken pabsb | Nate Begeman | 2008-02-09 | 1 | -129/+193 |
| * | Skeleton of insert and extract matching, more to come | Nate Begeman | 2008-02-09 | 1 | -2/+62 |
| * | The rest of the SSE4.1 intrinsic patterns that are obvious to me. Getting | Nate Begeman | 2008-02-04 | 1 | -8/+45 |
| * | Some more SSE 4.1 intrinsic patterns. | Nate Begeman | 2008-02-04 | 1 | -31/+94 |
| * | SSE 4.1 Intrinsics and detection | Nate Begeman | 2008-02-03 | 1 | -0/+95 |
| * | Significantly simplify and improve handling of FP function results on x86-32. | Chris Lattner | 2008-01-24 | 1 | -0/+8 |
| * | add some missing flags. | Chris Lattner | 2008-01-11 | 1 | -4/+16 |
| * | Start inferring side effect information more aggressively, and fix many bugs ... | Chris Lattner | 2008-01-10 | 1 | -5/+15 |
| * | remove explicit sets of 'neverHasSideEffects' that can now be | Chris Lattner | 2008-01-10 | 1 | -4/+4 |
| * | rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. | Chris Lattner | 2008-01-06 | 1 | -12/+12 |
| * | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 | 1 | -2/+2 |
| * | Fix JIT encoding for CMPSD as well. | Evan Cheng | 2007-12-20 | 1 | -4/+4 |
| * | Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I | Bill Wendling | 2007-12-17 | 1 | -8/+8 |
| * | Fix the JIT encoding of cmp*ss, which aborts with this assertion currently: | Chris Lattner | 2007-12-16 | 1 | -4/+4 |
| * | Make better use of instructions that clear high bits; fix various 2-wide shuf... | Evan Cheng | 2007-12-15 | 1 | -26/+57 |
