| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add hasSideEffects=0 to some shift and rotate instructions. None of which are... | Craig Topper | 2012-12-27 | 1 | -1/+5 |
| * | Add SARX/SHRX/SHLX code generation support | Michael Liao | 2012-09-26 | 1 | -0/+55 |
| * | Add RORX code generation support | Michael Liao | 2012-09-26 | 1 | -0/+23 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -3/+3 |
| * | Instruction scheduling itinerary for Intel Atom. | Andrew Trick | 2012-02-01 | 1 | -192/+287 |
| * | Intel style asm variant does not need '%' prefix. | Devang Patel | 2012-01-03 | 1 | -14/+14 |
| * | Add X86 SARX, SHRX, and SHLX instructions. | Craig Topper | 2011-10-23 | 1 | -18/+32 |
| * | Add X86 RORX instruction | Craig Topper | 2011-10-23 | 1 | -0/+21 |
| * | rework the rotate-by-1 instructions to be defined like the | Chris Lattner | 2010-11-06 | 1 | -16/+16 |
| * | integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight. | Chris Lattner | 2010-10-05 | 1 | -81/+249 |
| * | move 32-bit shift and rotates out to their own file. | Chris Lattner | 2010-10-05 | 1 | -0/+578 |
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