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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-41/+97
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-56/+359
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-0/+35
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-4/+4
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-171/+140
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Merging r195093:Bill Wendling2013-11-191-63/+17
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195093 | atrick | 2013-11-18 19:29:56 -0800 (Mon, 18 Nov 2013) | 4 lines Add an abstraction to handle patchpoint operands. Hard-coded operand indices were scattered throughout lowering stages and layers. It was super bug prone. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195112 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a size field to the stack map record to handle subregister spills.Andrew Trick2013-11-171-10/+27
| | | | | | | | Implementing this on bigendian platforms could get strange. I added a target hook, getStackSlotRange, per Jakob's recommendation to make this as explicit as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused arguments.Lang Hames2013-11-151-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194882 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor extension to llvm.experimental.patchpoint: don't require a call.Andrew Trick2013-11-141-11/+16
| | | | | | | | If a null call target is provided, don't emit a dummy call. This allows the runtime to reserve as little nop space as it needs without the requirement of emitting a call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194676 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower X86::MORESTACK_RET and X86::MORESTACK_RET_RESTORE_R10 inLang Hames2013-11-111-12/+12
| | | | | | | | | | | | | | | X86AsmPrinter::EmitInstruction, rather than X86MCInstLower::Lower. The aim is to improve the reusability of the X86MCInstLower class by making it more function-like. The X86::MORESTACK_RET_RESTORE_R10 pseudo broke the function model by emitting an extra instruction to the MCStreamer attached to the AsmPrinter. The patch should have no impact on generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194431 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmap] Materialize the jump address within the patchpoint noop slide.Juergen Ributzka2013-11-091-3/+22
| | | | | | | | | | | | | | | This patch moves the jump address materialization inside the noop slide. This enables patching of the materialization itself or its complete removal. This patch also adds the ability to define scratch registers that can be used safely by the code called from the patchpoint intrinsic. At least one scratch register is required, because that one is used for the materialization of the jump address. This patch depends on D2009. Differential Revision: http://llvm-reviews.chandlerc.com/D2074 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194306 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.Juergen Ributzka2013-11-081-8/+27
| | | | | | | | | | | | | | The idea of the AnyReg Calling Convention is to provide the call arguments in registers, but not to force them to be placed in a paticular order into a specified set of registers. Instead it is up tp the register allocator to assign any register as it sees fit. The same applies to the return value (if applicable). Differential Revision: http://llvm-reviews.chandlerc.com/D2009 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194293 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix unused variable warnings.Dan Gohman2013-10-311-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193823 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for stack map generation in the X86 backend.Andrew Trick2013-10-311-0/+124
| | | | | | Originally implemented by Lang Hames. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193811 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a helper getSymbol to AsmPrinter.Rafael Espindola2013-10-291-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
* The asm printer has a mangler. Don't keep a second pointer to it.Rafael Espindola2013-10-291-10/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193616 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Shrink certain forms of movsx.Benjamin Kramer2013-07-121-0/+35
| | | | | | | | | | | | In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186174 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-161-7/+1
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-101-17/+1
| | | | | | | | | | | | Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-011-1/+17
| | | | | | Very sorry, it was committed from the wrong branch by mistake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
* TMP: LEA64_32r fixingTim Northover2013-06-011-17/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-011-13/+4
| | | | | | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. This fixes a typo in the opcode field of the original patch, which should make the legact JIT work again (& adds test for that problem). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-311-4/+13
| | | | | | seems to have caused PR16192 and other JIT related failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183059 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-311-13/+4
| | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182991 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-301-10/+0
| | | | | | | | | | | | Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change zext moves to use sub-register infrastructure.Tim Northover2013-05-301-6/+0
| | | | | | | | | | | | 32-bit writes on amd64 zero out the high bits of the corresponding 64-bit register. LLVM makes use of this for zero-extension, but until now relied on custom MCLowering and other code to fixup instructions. Now we have proper handling of sub-registers, this can be done by creating SUBREG_TO_REG instructions at selection-time. Should be no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182921 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 code emitter support AVX encoded MRMDestReg instructions.Craig Topper2013-03-161-24/+33
| | | | | | | | Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded ↵Craig Topper2013-03-141-0/+42
| | | | | | register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177011 91177308-0d34-0410-b5e6-96231b3b80d8
* Two changes relevant to LEA and x32:David Sehr2013-02-011-1/+2
| | | | | | | | | | | | 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174208 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+4
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer2012-11-261-17/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168597 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer2012-11-261-39/+22
| | | | | | | | MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168587 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix setjmp on models with non-Small code model nor non-Static relocation modelMichael Liao2012-10-171-10/+8
| | | | | | | | | | | | - MBB address is only valid as an immediate value in Small & Static code/relocation models. On other models, LEA is needed to load IP address of the restore MBB. - A minor fix of MBB in MC lowering is added as well to enable target relocation flag being propagated into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166084 91177308-0d34-0410-b5e6-96231b3b80d8
* Move X86MCInstLower class definition into implementation file. It's not ↵Craig Topper2012-10-161-1/+25
| | | | | | needed outside. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166014 91177308-0d34-0410-b5e6-96231b3b80d8
* Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ↵Craig Topper2012-10-051-4/+0
| | | | | | ExpandPostRAPseudos and mark them as pseudos in the td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165302 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper2012-08-281-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper2012-08-281-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Chad Rosier2012-08-011-31/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a base register instead of an index register with the local dynamic model.Rafael Espindola2012-06-071-0/+8
| | | | | | Fixes pr13048. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-011-6/+31
| | | | | | | | | This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor data-in-code annotations.Jim Grosbach2012-05-181-2/+0
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157062 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-111-0/+1
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-2/+2
| | | | | | some superfluous forward declarations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the same CALL instructions for Windows as for everything else.Jakob Stoklund Olesen2012-02-161-6/+4
| | | | | | | The different calling conventions and call-preserved registers are represented with regmask operands that are added dynamically. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov2012-02-111-1/+3
| | | | | | | Patch by Kai Nacke! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachable in X86 Target directory.Craig Topper2012-02-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-181-0/+3
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
* Make X86 instruction selection use 256-bit VPXOR for build_vector of all ↵Craig Topper2012-01-131-0/+1
| | | | | | ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
* Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.Jakob Stoklund Olesen2011-11-291-4/+0
| | | | | | | | | Like V_SET0, these instructions are expanded by ExpandPostRA to xorps / vxorps so they can participate in execution domain swizzling. This also makes the AVX variants redundant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
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