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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-18/+26
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-19/+22
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update to LLVM 3.5a.Stephen Hines2014-04-241-4/+8
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* I'm starting to commit KNL backend. I'll push patches one-by-one. This patch ↵Elena Demikhovsky2013-07-241-17/+65
| | | | | | | | | includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31. The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187030 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: sub_xmm registers are 128 bits wide.Ahmed Bougacha2013-06-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183103 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-311-5/+5
| | | | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
* Add register encoding support in X86 backendMichael Liao2012-10-041-245/+251
| | | | | | | | | | - Add 'HwEncoding' for X86 registers and call getEncodingValue() to retrieve their encoding values. - This's the first step to adopt new scheme. Furthur revising is onging. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165241 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the X86 sub_ss and sub_sd sub-register indexes completely.Jakob Stoklund Olesen2012-07-261-6/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160833 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-041-78/+19
| | | | | | This information in now computed by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Don't emit conditional floating point moves on when targeting ↵Benjamin Kramer2012-04-271-0/+7
| | | | | | | | | | | | | | | | pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the YMM_HI_6_15 hack.Jakob Stoklund Olesen2012-02-161-7/+0
| | | | | | | | | Call clobbers are now represented with register mask operands. The regmask can easily represent the fact that xmm6 is call-preserved while ymm6 isn't. This is automatically computed by TableGen from the CalleeSavedRegs containing xmm6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150709 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle call-clobbered ymm registers on Win64.Jakob Stoklund Olesen2012-01-261-0/+7
| | | | | | | | | | | | | | The Win64 calling convention has xmm6-15 as callee-saved while still clobbering all ymm registers. Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the ymm registers, and mark that as call-clobbered. This allows live xmm registers across calls. This hack wouldn't be necessary with RegisterMask operands representing the call clobbers, but they are not quite operational yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-181-1/+1
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper2011-10-071-14/+4
| | | | | | 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-061-0/+17
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
* Add v16i16 type to VR256 classBruno Cardoso Lopes2011-07-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135658 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen2011-06-281-9/+16
| | | | | | | | | | | | | | | | | | | | Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134018 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch x86 to using AltOrders instead of MethodBodies.Jakob Stoklund Olesen2011-06-181-67/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133325 91177308-0d34-0410-b5e6-96231b3b80d8
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-60/+41
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-200/+2
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag unallocatable register classes instead of giving them emptyJakob Stoklund Olesen2011-06-021-20/+2
| | | | | | allocation orders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce the DwarfRegAlias class for declaring that two registers have theRafael Espindola2011-05-301-16/+16
| | | | | | | | | | same dwarf number. This will be used for creating a dwarf number to register mapping. The only case that needs this so far is the XMM/YMM registers that unfortunately do have the same numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they areRafael Espindola2011-05-301-9/+9
| | | | | | subregisters of the 64 bit ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132313 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 132187 back now that the real problem is fixed.Rafael Espindola2011-05-281-45/+45
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132238 91177308-0d34-0410-b5e6-96231b3b80d8
* It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while ↵Rafael Espindola2011-05-271-45/+45
| | | | | | I check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132230 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a GR32_NOREX_NOSP register class and fix a bug where ↵Cameron Zwarich2011-05-271-1/+9
| | | | | | | | | getMatchingSuperRegClass() was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132225 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete MethodBodies that only filtered reserved registers.Jakob Stoklund Olesen2011-05-271-111/+0
| | | | | | | The register allocators know to filter reserved registers from the allocation orders, so we don't need all of this boilerplate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132199 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dwarf numbers from subregs. We should use DW_OP_bit_piece toRafael Espindola2011-05-271-45/+45
| | | | | | | | refer to them. I tested this with both check-all and the gdb testsuite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132187 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC ↵Cameron Zwarich2011-05-211-1/+1
| | | | | | | | | code. It is already in GR64 for the same reasons. Since it isn't allocatable it can't cause any problems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131787 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-201-7/+13
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: Tweak win64's tailcall.NAKAMURA Takumi2011-01-261-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix whitespace.NAKAMURA Takumi2011-01-261-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-10/+10
| | | | | | and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-23/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
* random acts of tidiness.Chris Lattner2010-11-141-10/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119049 91177308-0d34-0410-b5e6-96231b3b80d8
* lets go all meta and define new X86 type wrappers that declare the associatedChris Lattner2010-10-061-22/+12
| | | | | | | | gunk that goes along with an MVT (e.g. reg class, preferred load operation, memory operand) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115727 91177308-0d34-0410-b5e6-96231b3b80d8
* associate the instruction suffix letter with the integer gpr Chris Lattner2010-10-051-12/+22
| | | | | | | | register class, and use this to simplify use of BinOpRR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115716 91177308-0d34-0410-b5e6-96231b3b80d8
* Massive rewrite of MMX: Dale Johannesen2010-09-301-1/+1
| | | | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"Chris Lattner2010-09-221-2/+10
| | | | | | | Teaching the code generator about CR8-15, how to rex them up, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
* Make %EFLAGS unallocatable.Jakob Stoklund Olesen2010-08-311-0/+11
| | | | | | | No CCR virtual registers should exist, and %EFLAGS is used in ways that can surprise RegAllocFast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112650 91177308-0d34-0410-b5e6-96231b3b80d8
* Support x86 "eiz" and "riz" pseudo index registers in the assembler.Bruno Cardoso Lopes2010-07-241-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes2010-07-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
* Declare YMM subregisters in the right way! Thanks JakobBruno Cardoso Lopes2010-07-091-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108022 91177308-0d34-0410-b5e6-96231b3b80d8
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-091-8/+25
| | | | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
* rip out even more sporadic v2f32 support.Chris Lattner2010-07-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-71/+16
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-16/+71
| | | | | | This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-71/+16
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-251-8/+8
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-63/+63
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
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