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* Whitespace.NAKAMURA Takumi2013-03-251-160/+160
* x86 -- add the XTEST instructionDave Zarzycki2013-03-254-31/+30
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-251-7/+20
* Add a WriteMicrocoded for ancient microcoded instructions.Jakob Stoklund Olesen2013-03-212-0/+7
* Model prefetches and barriers as loads.Jakob Stoklund Olesen2013-03-201-1/+4
* Add a catch-all WriteSystem SchedWrite type.Jakob Stoklund Olesen2013-03-203-1/+28
* Annotate the remaining SSE MOV instructions.Jakob Stoklund Olesen2013-03-201-25/+45
* Annotate SSE horizontal and integer instructions.Jakob Stoklund Olesen2013-03-201-16/+26
* Correct cost model for vector shift on AVX2Michael Liao2013-03-201-0/+23
* Add some missing SSE annotations.Jakob Stoklund Olesen2013-03-201-8/+18
* Annotate remaining IIC_BIN_* instructions.Jakob Stoklund Olesen2013-03-201-5/+10
* Fix PR15296Michael Liao2013-03-201-119/+199
* Mark all variable shifts needing customizingMichael Liao2013-03-201-28/+29
* Move scalar immediate shift lowering into a dedicated funcMichael Liao2013-03-201-5/+20
* Annotate various null idioms with SchedRW lists.Jakob Stoklund Olesen2013-03-191-4/+4
* Annotate SSE float conversions with SchedRW lists.Jakob Stoklund Olesen2013-03-191-60/+81
* Annotate X86InstrCMovSetCC.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-4/+5
* [ms-inline asm] Move the immediate asm rewrite into the target specificChad Rosier2013-03-191-10/+4
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-192-8/+13
* [ms-inline asm] Create a helper function, CreateMemForInlineAsm, that createsChad Rosier2013-03-191-36/+49
* Remove an invalid and unnecessary Pat pattern from the X86 backend:Ulrich Weigand2013-03-191-3/+0
* Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.Nadav Rotem2013-03-192-4/+19
* Annotate X86InstrExtension.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-26/+39
* Annotate a lot of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-26/+60
* [ms-inline asm] Move the size directive asm rewrite into the target specificChad Rosier2013-03-191-44/+33
* [ms-inline asm] Avoid emitting a redundant sizing directive, if we've alreadyChad Rosier2013-03-181-2/+3
* Add SchedRW annotations to most of X86InstrSSE.td.Jakob Stoklund Olesen2013-03-181-186/+280
* Annotate X86 arithmetic instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-181-60/+112
* TLS support for MinGW targets.Anton Korobeynikov2013-03-181-7/+8
* Post process ADC/SBB and use a shorter encoding if they use a sign extended i...Craig Topper2013-03-181-0/+6
* Refactor some duplicated code into helper functions.Craig Topper2013-03-181-229/+55
* Add X86 code emitter support AVX encoded MRMDestReg instructions.Craig Topper2013-03-163-32/+63
* Define more SchedWrites for annotating X86 instructions.Jakob Stoklund Olesen2013-03-161-11/+57
* Silence anonymous type in anonymous union warnings.Eric Christopher2013-03-151-23/+28
* Unaligned loads should use the VMOVUPS opcode.Nadav Rotem2013-03-141-1/+1
* Prepare for adding InstrSchedModel annotations to X86 instructions.Jakob Stoklund Olesen2013-03-141-0/+26
* [fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handleChad Rosier2013-03-141-0/+3
* Fix the name of a variable to match its declaration. Fixes build failure from...Craig Topper2013-03-141-1/+1
* Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit ...Craig Topper2013-03-142-0/+13
* Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded regist...Craig Topper2013-03-141-0/+42
* Fix PR15309Michael Liao2013-03-141-1/+2
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-111-1/+1
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-081-1/+7
* X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.Benjamin Kramer2013-03-071-0/+5
* Fix two remaining issue after fixing PR15355 when CMOV is not availableMichael Liao2013-03-071-6/+22
* Fix PR15355Michael Liao2013-03-061-102/+182
* The current X86 NOP padding uses one long NOP followed by the remainder inDavid Sehr2013-03-051-12/+12
* Bypass Slow DividesPreston Gurd2013-03-041-2/+5
* X86 cost model: Adjust cost for custom lowered vector multipliesArnold Schwaighofer2013-03-021-5/+29
* Fix PR10475Michael Liao2013-03-012-2/+2
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