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* Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.Bill Wendling2012-03-101-5/+5
* Do not custom lower i64 nodes if i64 is not a legal type. Move lines that setAkira Hatanaka2012-03-101-11/+14
* Lower SETCC nodes during legalization. Previously, it was lowered in DAG comb...Akira Hatanaka2012-03-092-20/+16
* Remove unused header files.Akira Hatanaka2012-03-091-2/+0
* Add the missing call to Error when a bad X86 scale expression is parsed.Kevin Enderby2012-03-091-1/+3
* Fix the x86 disassembler to at least print the lock prefix if it is the firstKevin Enderby2012-03-091-0/+7
* Use uint16_t to store opcodes in static tables in X86 backend.Craig Topper2012-03-093-24/+30
* Fix undefined behavior in the Mips backend.Ahmed Charles2012-03-092-15/+15
* Fix a regression from r147481.Chad Rosier2012-03-092-1/+8
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-1/+1
* Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy2012-03-082-9/+9
* Invoke setTargetDAGCombine for SELECT.Akira Hatanaka2012-03-081-0/+1
* Swap the operands of a select node if the false (the second) operand is 0.Akira Hatanaka2012-03-081-0/+35
* Set minimum function alignment to 3 if target is Mips64.Akira Hatanaka2012-03-081-1/+1
* This patch eliminates redundant instructions that produce 0.Akira Hatanaka2012-03-081-1/+50
* ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach2012-03-081-2/+2
* [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point Chad Rosier2012-03-071-4/+2
* ARM pre-v6 assembly parsing for umull/smull.Jim Grosbach2012-03-071-0/+10
* ARM pre-v6 alias for 'nop' to 'mov r0, r0'Jim Grosbach2012-03-071-0/+4
* Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach2012-03-071-6/+0
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-065-39/+58
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-068-168/+117
* Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman2012-03-061-13/+13
* Tidy up. Kill some dead code.Jim Grosbach2012-03-062-10/+0
* Allow the same types in DPair as in QPR.Jakob Stoklund Olesen2012-03-061-1/+2
* Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby2012-03-061-7/+7
* Convert PowerPC to register mask operands.Roman Divacky2012-03-066-122/+52
* Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen2012-03-061-0/+4
* Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames2012-03-064-11/+17
* ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach2012-03-051-0/+8
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-055-26/+91
* ARM Remove a bit of dead code.Jim Grosbach2012-03-052-14/+0
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-0511-246/+239
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-0518-27/+37
* Address Evan's comments for r151877.Chad Rosier2012-03-051-7/+6
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-057-39/+41
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce stati...Craig Topper2012-03-054-9/+9
* Make aliases for shld and shrd match gas. PR12173.Eli Friedman2012-03-051-14/+14
* Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen2012-03-041-14/+12
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-045-11/+11
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces s...Craig Topper2012-03-043-15/+15
* Use uint16_t to store registers in callee saved register tables to reduce siz...Craig Topper2012-03-0424-45/+45
* Use uint8_t instead of enums to store values in X86 disassembler table. Shave...Craig Topper2012-03-042-4/+4
* Prevent obscure and incorrect tail-call optimization.Chad Rosier2012-03-021-0/+5
* Neuter the optimization I implemented with r107852 and r108258 which turn someEvan Cheng2012-03-011-8/+12
* Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister().Jakob Stoklund Olesen2012-03-011-0/+5
* ARM use the right opcode for FP<->Integer move in fast-isel.Jim Grosbach2012-03-011-2/+2
* Minimal changes for LLVM to compile under VS11.Michael J. Spencer2012-03-011-0/+4
* Changes for migrating to using register mask operands.Akira Hatanaka2012-03-016-48/+45
* Change ARMInstPrinter::printPredicateOperand() so it will not abort if itKevin Enderby2012-03-011-1/+4
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