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* Tighten up ARM reglist validation a bit.Jim Grosbach2011-08-221-11/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another batch of VLD/VST decoding crashes discovered by randomized testing.Owen Anderson2011-08-221-16/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct writeback handling of duplicating VLD instructions. Discovered by ↵Owen Anderson2011-08-221-4/+4
| | | | | | randomized testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up predicates on ARM target instruction aliases.Jim Grosbach2011-08-224-61/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add ↵Owen Anderson2011-08-221-1/+1
| | | | | | more tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
* Cast through intptr_t, ISO C++ requires it.Benjamin Kramer2011-08-201-5/+3
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* Remove the VMOVQQ pseudo instruction.Chad Rosier2011-08-203-44/+8
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* Remove VMOVQQQQ pseudo instruction.Chad Rosier2011-08-201-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138174 91177308-0d34-0410-b5e6-96231b3b80d8
* Add <imp-def> operands to QQ and QQQQ stack loads.Jakob Stoklund Olesen2011-08-201-2/+4
| | | | | | | | This pleases the register scavenger and brings test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to working with -verify-machineinstrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8
* VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.Chad Rosier2011-08-202-56/+31
| | | | | | | Therefore, rather then generate a pseudo instruction, which is later expanded, generate the necessary instructions in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb parsing and encoding support for NOP.Jim Grosbach2011-08-193-1/+15
| | | | | | | The irony is not lost that this is not a completely trivial patchset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is notAkira Hatanaka2011-08-191-14/+9
| | | | | | | | needed for Mips32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138132 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for NEG.Jim Grosbach2011-08-191-1/+1
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* Fix NEG aliasJim Grosbach2011-08-191-1/+1
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* Be more lenient on tied operand matching for MUL.Jim Grosbach2011-08-191-4/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-write part of VEX encoding logic, to be more easy to read! Also fixBruno Cardoso Lopes2011-08-191-58/+82
| | | | | | a bug and add a testcase! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tests.Jim Grosbach2011-08-191-0/+4
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* Thumb assembly parsing and encoding for MUL.Jim Grosbach2011-08-192-5/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for MOV.Jim Grosbach2011-08-193-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Tab character.Jim Grosbach2011-08-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138072 91177308-0d34-0410-b5e6-96231b3b80d8
* Tab characters.Jim Grosbach2011-08-191-2/+2
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* Thumb assembly parsing and encoding for LSL(immediate).Jim Grosbach2011-08-192-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDRSB and LDRSH.Jim Grosbach2011-08-191-0/+1
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* Thumb assembly parsing and encoding for LDRH.Jim Grosbach2011-08-192-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDRB.Jim Grosbach2011-08-192-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDR(literal).Jim Grosbach2011-08-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDR(immediate) form T2.Jim Grosbach2011-08-192-1/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
* Use helper function to check for low registers.Jim Grosbach2011-08-191-1/+1
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* Thumb assembly parsing and encoding for LDR(immediate) form T1.Jim Grosbach2011-08-192-1/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
* Add explanatory comment.Jim Grosbach2011-08-191-0/+5
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* Have SPU backend use the external TCE scheduler, if the library is loaded as aKalle Raiskila2011-08-191-0/+11
| | | | | | | | | module. Patch by Pekka Jääskeläinen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138037 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TB encoding to VEX versions of SSE fp logical operations to fix disassemblerCraig Topper2011-08-191-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10677. Initial patch and idea by Peter Cooper but I've changed theBruno Cardoso Lopes2011-08-191-3/+8
| | | | | | implementation! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
* Make a bunch of symbols private.Benjamin Kramer2011-08-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138025 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operandsBruno Cardoso Lopes2011-08-181-31/+64
| | | | | | | | | | | | | | | | | | instead of 2. They were already defined this way in their regular version, but not for the intrinsics versions (*_Int), and that would work for assembly emission but not for object code, since a MachineOperand would be missing. This commit fix PR10697. Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for memory versions because sse_load_f32/sse_load_f64 operand need special handling and don't work like regular "addr" operands. There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly removing them as I step through, but hope we can get rid of these someday, they are really annoying :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138012 91177308-0d34-0410-b5e6-96231b3b80d8
* Use subword loads instead of a 4-byte load when the size of a structure (or aAkira Hatanaka2011-08-181-26/+73
| | | | | | | | piece of it) that is being passed by value is smaller than a word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138007 91177308-0d34-0410-b5e6-96231b3b80d8
* STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST ↵Owen Anderson2011-08-181-0/+4
| | | | | | | | | for the purposes of decoding all operands except the predicate. Found by randomized testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ↵Owen Anderson2011-08-181-8/+42
| | | | | | have it unset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
* Remember to fill in some operands so we can print _something_ coherent even ↵Owen Anderson2011-08-181-1/+4
| | | | | | when decoding the CPS instruction soft-fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137997 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve handling of failure and unpredictable cases for CPS, STR, and SMLA ↵Owen Anderson2011-08-181-11/+18
| | | | | | | | | instructions. Fixes a large class of disassembler crashes found by randomized testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach2011-08-183-5/+33
| | | | | | | | | Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
* Make IsShiftedMask a static function rather than defining it in anAkira Hatanaka2011-08-181-16/+14
| | | | | | | | anonymous namespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137975 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for CMP.Jim Grosbach2011-08-181-1/+1
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* Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.Jim Grosbach2011-08-182-25/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137956 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Thumb blx instruction fixup has same data range as bl.Jim Grosbach2011-08-181-1/+1
| | | | | | | | | | These fixups are handled poorly in general, and should have a single contiguous range of bits per fixup type, but that's not how they're currently organized, so for now in complex ones like for blx, we just tell the emitter it's OK for the fixup to munge any bit it wants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137947 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 columns.Jim Grosbach2011-08-181-1/+1
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* Clenup and fix encoding for Mips ins and ext instructionBruno Cardoso Lopes2011-08-181-17/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137943 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing 'break'.Jim Grosbach2011-08-181-0/+1
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* Add intrinsics for SETEV, GETED, GETET.Richard Osborne2011-08-181-7/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137938 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup vector logical ops in AVX and add use int versions for simpleBruno Cardoso Lopes2011-08-181-20/+20
| | | | | | v2i64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137919 91177308-0d34-0410-b5e6-96231b3b80d8
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