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* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+78
* Intel syntax: There is no need to create unary expr for simple negative displ...Devang Patel2012-01-191-1/+1
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, i...Devang Patel2012-01-191-0/+114
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+3
* Folding table additions and fixes for AVX.Craig Topper2012-01-191-9/+21
* Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.Craig Topper2012-01-193-129/+80
* ARM assembly diagnostic caret in better position for FPImm.Jim Grosbach2012-01-191-3/+4
* Thumb2 relaxation for tADR to t2ADR.Jim Grosbach2012-01-191-0/+2
* Add comment and fix range check in condition.Jim Grosbach2012-01-191-1/+3
* - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointingEvan Cheng2012-01-191-1/+2
* Add a TargetOption for disabling tail calls.Nick Lewycky2012-01-191-1/+4
* Rename Finalizebundle to finalizeBundle to conform to coding guideline.Evan Cheng2012-01-191-1/+1
* Add experimental -x86-use-regmask command line option.Jakob Stoklund Olesen2012-01-181-0/+12
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-186-1/+17
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-183-0/+69
* Process instructions after match to select alternative encoding which may be ...Devang Patel2012-01-181-16/+87
* Replace FIXME with explanatory comment.Jim Grosbach2012-01-181-1/+2
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-9/+20
* Rename pattern for clarity.Jim Grosbach2012-01-181-4/+3
* Tidy up. 80 columns.Jim Grosbach2012-01-181-13/+13
* Tidy up. MCAsmBackend naming conventions.Jim Grosbach2012-01-185-38/+38
* Thumb2 load/store fixups don't set the thumb bit.Jim Grosbach2012-01-181-4/+8
* Move some ARM specific MCAssmebler bits into the ARMAsmBackend.Jim Grosbach2012-01-181-0/+15
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-185-2/+6
* Implement ARMBaseRegisterInfo::getCallPreservedMask().Jakob Stoklund Olesen2012-01-173-19/+17
* Move X86 callee saved register lists to the X86CallConv .td file.Jakob Stoklund Olesen2012-01-173-37/+37
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-3/+3
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+4
* Untabify.Devang Patel2012-01-171-12/+12
* Intel syntax: Do not unncessarily create plus expression for memory operand d...Devang Patel2012-01-171-2/+1
* Intel syntax: Robustify memory operand parsing.Devang Patel2012-01-171-51/+113
* Fix warning.Nadav Rotem2012-01-171-1/+1
* Fix 11769.Nadav Rotem2012-01-171-0/+7
* Remove unnecessary AVX check from an assert. hasSSE2 is enough.Craig Topper2012-01-171-2/+1
* Moving options declarations around.Andrew Trick2012-01-171-8/+0
* Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. ...Craig Topper2012-01-171-0/+5
* Removing unused default switch cases in switches over enums that already acco...David Blaikie2012-01-163-10/+1
* Cleanup PPC RLWINM8 vs RLWINMHal Finkel2012-01-161-1/+1
* Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.Eli Friedman2012-01-161-1/+1
* Get rid of unused codegen-only instruction.Eli Friedman2012-01-162-12/+0
* Give priority to AVX over SSE for 128-bit floating point unpck instructions.Craig Topper2012-01-161-34/+34
* Refactor variables unused under non-assert builds (& remove two entirely unus...David Blaikie2012-01-161-2/+2
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-1/+22
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through Code...Benjamin Kramer2012-01-153-87/+50
* Fix the memop type on a couple 256-bit AVX instructions that were using f128m...Craig Topper2012-01-141-4/+4
* Add a bunch of AVX instructions to the folding tables. Also fixed the alignme...Craig Topper2012-01-141-69/+139
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-141-0/+5
* Fix pasto from r146196.Chad Rosier2012-01-141-2/+2
* Use RegisterTuples to generate pseudo-registers.Jakob Stoklund Olesen2012-01-134-45/+51
* Revert r148131, it was committed before it was ready.Devang Patel2012-01-131-46/+40