| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fixes an issue reported by -verify-machineinstrs. | Rafael Espindola | 2011-10-26 | 2 | -6/+7 |
| * | ARM parse parenthesized expressions for label references. | Jim Grosbach | 2011-10-26 | 1 | -0/+1 |
| * | This commit introduces two fake instructions MORESTACK_RET and | Rafael Espindola | 2011-10-26 | 3 | -21/+39 |
| * | Make sure short memsets on ARM lower to stores, even when optimizing for size. | Lang Hames | 2011-10-26 | 1 | -0/+2 |
| * | Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern. | Jim Grosbach | 2011-10-26 | 1 | -1/+1 |
| * | Revert r142530 at least temporarily while a discussion is had on llvm-commits... | James Molloy | 2011-10-26 | 1 | -5/+2 |
| * | Use a worklist to prevent the iterator from becoming invalidated because of t... | Bill Wendling | 2011-10-26 | 1 | -3/+4 |
| * | Revert part of r142530. The patch potentially hurts performance especially | Evan Cheng | 2011-10-26 | 1 | -3/+3 |
| * | Corrects previously incorrect $sp change in MipsCompilationCallback. | Bruno Cardoso Lopes | 2011-10-25 | 1 | -7/+7 |
| * | ARM assembly parsing and encoding for VLD1 with writeback. | Jim Grosbach | 2011-10-25 | 3 | -17/+33 |
| * | Remove the Blackfin backend. | Dan Gohman | 2011-10-25 | 37 | -4415/+0 |
| * | Remove the SystemZ backend. | Dan Gohman | 2011-10-24 | 37 | -6279/+0 |
| * | Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. | Jim Grosbach | 2011-10-24 | 3 | -4/+0 |
| * | ARM assembly parsing and encoding for VLD1 w/ writeback. | Jim Grosbach | 2011-10-24 | 4 | -21/+33 |
| * | Don't crash on variable insertelement on ARM. PR10258. | Eli Friedman | 2011-10-24 | 1 | -0/+11 |
| * | ARMConstantPoolMBB::print should print BB number. | Evan Cheng | 2011-10-24 | 1 | -0/+1 |
| * | ARM assembly parsing and encoding for VLD1 w/ writeback. | Jim Grosbach | 2011-10-24 | 2 | -0/+38 |
| * | ARM refactor am6offset usage for VLD1. | Jim Grosbach | 2011-10-24 | 5 | -71/+181 |
| * | Add support to the old JIT for acquire/release loads and stores on x86. PR11... | Eli Friedman | 2011-10-24 | 1 | -9/+24 |
| * | Fix a NEON disassembly case that was broken in the recent refactorings. As m... | Owen Anderson | 2011-10-24 | 1 | -6/+0 |
| * | Change this overloaded use of Sched::Latency to be an overloaded | Dan Gohman | 2011-10-24 | 1 | -2/+2 |
| * | Remove the explicit request for "Latency" scheduling from MSP430, | Dan Gohman | 2011-10-24 | 1 | -1/+0 |
| * | Thumb2 LDM instructions can target PC. Make sure to encode it. | Jim Grosbach | 2011-10-24 | 1 | -8/+4 |
| * | Add X86 SARX, SHRX, and SHLX instructions. | Craig Topper | 2011-10-23 | 1 | -18/+32 |
| * | Add X86 RORX instruction | Craig Topper | 2011-10-23 | 5 | -0/+36 |
| * | Add X86 MULX instruction for disassembler. | Craig Topper | 2011-10-23 | 1 | -0/+24 |
| * | Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 ... | Craig Topper | 2011-10-22 | 1 | -5/+5 |
| * | Move various generated tables into read-only memory, fixing up const correctn... | Benjamin Kramer | 2011-10-22 | 3 | -11/+12 |
| * | Fix pr11193. | Nadav Rotem | 2011-10-22 | 1 | -3/+0 |
| * | The different flavors of ARM have different valid subsets of registers. Check | Bill Wendling | 2011-10-22 | 1 | -3/+13 |
| * | Assembly parsing for 4-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 | 3 | -36/+18 |
| * | Assembly parsing for 2-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 | 4 | -30/+46 |
| * | Assembly parsing for 4-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 6 | -31/+38 |
| * | Assembly parsing for 3-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 6 | -22/+37 |
| * | ARM VLD parsing and encoding. | Jim Grosbach | 2011-10-21 | 6 | -247/+276 |
| * | Don't automatically set the "fc" bits on MSR instructions if the user didn't ... | Owen Anderson | 2011-10-21 | 1 | -3/+7 |
| * | Nuke an #if0 that got accidentally left in. | Jim Grosbach | 2011-10-21 | 1 | -31/+0 |
| * | whitespace. | Jim Grosbach | 2011-10-21 | 1 | -1/+1 |
| * | Remove some outdated comments. | Jim Grosbach | 2011-10-21 | 1 | -11/+11 |
| * | Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with ... | Craig Topper | 2011-10-21 | 3 | -11/+71 |
| * | Fix unused variable warning. | Richard Smith | 2011-10-21 | 1 | -1/+1 |
| * | Revert r142618, r142622, and r142624, which were based on an incorrect readin... | Owen Anderson | 2011-10-20 | 1 | -42/+4 |
| * | Disable the PPC hazard recognizer. It currently only supports | Dan Gohman | 2011-10-20 | 1 | -2/+8 |
| * | Separate out ARM MSR instructions into M-class versions and AR-class versions... | Owen Anderson | 2011-10-20 | 1 | -4/+42 |
| * | Add missing operand. <rdar://problem/10313323> | Bill Wendling | 2011-10-20 | 1 | -1/+2 |
| * | Haven't yet found a nice way to handle TargetData verification in the | Lang Hames | 2011-10-20 | 1 | -25/+88 |
| * | Tidy up. Trailing whitespace. | Jim Grosbach | 2011-10-20 | 1 | -2/+2 |
| * | ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. | Jim Grosbach | 2011-10-20 | 1 | -4/+4 |
| * | ARM VTBX (one register) assembly parsing and encoding. | Jim Grosbach | 2011-10-20 | 1 | -3/+3 |
| * | Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( | Chad Rosier | 2011-10-20 | 3 | -32/+11 |
