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* This patch makes the following changes necessary for MIPS' direct code emission.Akira Hatanaka2011-11-236-55/+236
* This patch addresses gp relative fixups/relocations for jump tables.Akira Hatanaka2011-11-231-1/+7
* X86: Use btq for bit tests if the immediate can't be encoded in 32 bits.Benjamin Kramer2011-11-231-1/+9
* I added several lines in X86 code generator that allow to choose Elena Demikhovsky2011-11-231-15/+46
* Fix PR11422.Jakob Stoklund Olesen2011-11-231-1/+4
* add basic PPC register-pressure feedback; adjust the vaarg test to match the ...Hal Finkel2011-11-224-5/+28
* More fixes to the X86InstComments for shuffle instructions. In particular add...Craig Topper2011-11-223-44/+60
* Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors cor...Craig Topper2011-11-224-21/+73
* Add methods for querying minimum SSE version along with AVX. Simplifies all t...Craig Topper2011-11-222-43/+38
* Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.Craig Topper2011-11-214-84/+30
* Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if ...Craig Topper2011-11-214-47/+115
* Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and us...Craig Topper2011-11-211-8/+42
* Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instruc...Craig Topper2011-11-202-45/+45
* Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.Craig Topper2011-11-194-16/+33
* Remove some of the special classes that worked around an old tablegen limitat...Craig Topper2011-11-191-100/+50
* Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove t...Craig Topper2011-11-192-74/+42
* Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add...Craig Topper2011-11-194-3/+62
* Collapse X86 PSIGNB/PSIGNW/PSIGND node types.Craig Topper2011-11-194-33/+18
* Extend VPBLENDVB and VPSIGN lowering to work for AVX2.Craig Topper2011-11-193-111/+127
* Remove unused parameters from the AVX maskmov classes.Craig Topper2011-11-191-12/+6
* Add AVX2 vpbroadcast supportNadav Rotem2011-11-182-28/+62
* Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work...Chad Rosier2011-11-181-3/+5
* Add TODO comment.Chad Rosier2011-11-171-0/+2
* Fix SSE/AVX integer comparison patterns to understand that all integer vector...Craig Topper2011-11-171-24/+42
* Dead code.Chad Rosier2011-11-171-14/+0
* Remove seemingly unnecessary duplicate VROUND definitions.Craig Topper2011-11-171-80/+4
* Add support for custom names for library functions in TargetLibraryInfo. Add...Eli Friedman2011-11-171-0/+25
* Don't unconditionally set the kill flag.Chad Rosier2011-11-171-1/+1
* Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I...Eli Friedman2011-11-171-1/+1
* Generalize the fixup info for ARM mode.Jim Grosbach2011-11-161-2/+2
* Lower 64-bit constant pool node.Akira Hatanaka2011-11-161-8/+12
* Lower 64-bit block address.Akira Hatanaka2011-11-161-9/+11
* Fix encoding of NOP used for padding in ARM mode .align.Jim Grosbach2011-11-161-1/+1
* Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpoolAkira Hatanaka2011-11-162-7/+24
* 64-bit jump register instruction.Akira Hatanaka2011-11-162-6/+7
* Another missing X86ISD::MOVLPD pattern. rdar://10450317Evan Cheng2011-11-161-0/+2
* ARM assembly parsing for shifted register operands for MOV instruction.Jim Grosbach2011-11-161-0/+2
* Clean up debug printing of ARM shifted operands.Jim Grosbach2011-11-161-9/+6
* ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.Jim Grosbach2011-11-161-0/+12
* ARM assembly parsing for RRX mnemonic.Jim Grosbach2011-11-162-1/+16
* Added missing comment about new custom lowering of DEC64Pete Cooper2011-11-161-0/+12
* Check to make sure we can select the instruction before trying to put theChad Rosier2011-11-161-6/+6
* ARM mode aliases for bitwise instructions w/ register operands.Jim Grosbach2011-11-162-0/+38
* Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.Bob Wilson2011-11-161-1/+1
* lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp al...NAKAMURA Takumi2011-11-161-2/+2
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-1636-218/+243
* Fix the execution domain on a bunch of SSE/AVX instructions.Craig Topper2011-11-161-91/+157
* Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>Bob Wilson2011-11-164-74/+4
* Remove code to enable execution dependency fix pass on VR256. VR128 is suffic...Craig Topper2011-11-161-9/+3
* Add FIXME comment.Chad Rosier2011-11-161-0/+2
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