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* Validate target data layout strings.Lang Hames2011-10-171-25/+88
* Use a SmallVector for intrinsic argument types.Benjamin Kramer2011-10-172-2/+2
* Don't renumber the blocks here. This could cause problems later on if anotherBill Wendling2011-10-171-3/+1
* Pseudoinstructions should not be less constrained than the instruction they areCameron Zwarich2011-10-171-6/+6
* Tidy up organization.Jim Grosbach2011-10-171-8/+4
* Add a call to EmitSjLjDispatchBlock.Bill Wendling2011-10-171-0/+8
* Fix improperly formed assert() call.Jim Grosbach2011-10-171-1/+1
* Add definitions of conditional moves with 64-bit operands. Comment out code forAkira Hatanaka2011-10-173-75/+130
* Revert change to function alignment b/c existing logic was fineHal Finkel2011-10-171-10/+3
* Removed set, but unused variables.Chad Rosier2011-10-172-12/+0
* Move class and instruction definitions for conditional moves to a seperate file.Akira Hatanaka2011-10-174-106/+112
* Revert change made in r142205.Akira Hatanaka2011-10-171-2/+2
* Redefine count-leading 0s and 1s instructions.Akira Hatanaka2011-10-172-20/+17
* Redefine mfhi/lo and mthi/lo instructions.Akira Hatanaka2011-10-172-35/+16
* Redefine multiply and divide instructions.Akira Hatanaka2011-10-172-25/+26
* Add definition of a base class for logical shift/rotate instructions with twoAkira Hatanaka2011-10-172-20/+12
* Remove >80-col line and unicodeHal Finkel2011-10-171-2/+2
* Add definition of a base class for logical shift/rotate immediate instructionsAkira Hatanaka2011-10-172-27/+33
* Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.Akira Hatanaka2011-10-173-9/+11
* Fix CMake build.Michael J. Spencer2011-10-171-1/+0
* svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cppDevang Patel2011-10-172-220/+2
* Instructions for Book E PPC should be word aligned, set function alignment to...Hal Finkel2011-10-171-3/+10
* Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means ...Craig Topper2011-10-172-24/+19
* Add comment explaining that the order of processing doesn't matter here.Bill Wendling2011-10-171-0/+1
* Add PPC 440 scheduler and some associated tests (new files)Hal Finkel2011-10-171-0/+568
* Add PPC 440 scheduler and some associated testsHal Finkel2011-10-179-2/+53
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-165-13/+42
* Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.Benjamin Kramer2011-10-161-9/+14
* X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print...Benjamin Kramer2011-10-161-3/+4
* Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there wasNadav Rotem2011-10-161-3/+5
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-167-50/+56
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMR...Craig Topper2011-10-162-12/+25
* Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.Cameron Zwarich2011-10-161-1/+3
* Fix an obvious typo found when looking at nearby code.Cameron Zwarich2011-10-161-1/+1
* Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does...Chris Lattner2011-10-161-6/+13
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3...Craig Topper2011-10-163-18/+54
* Add X86 feature detection support for BMI instructions. Added new cpuid funct...Craig Topper2011-10-163-18/+107
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ...Craig Topper2011-10-153-17/+46
* The CELL backend cannot select patterns for vector trunc-store and shl on v2...Nadav Rotem2011-10-151-0/+9
* ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when pro...Nadav Rotem2011-10-151-0/+2
* SmallVector -> arrayBenjamin Kramer2011-10-151-3/+3
* Mark tADDrSPi as having side effects again.Jakob Stoklund Olesen2011-10-151-3/+3
* Thumb1 does not support dynamic stack realignment.Chad Rosier2011-10-151-0/+5
* Mark registers as DEAD because they're really just clobbers.Bill Wendling2011-10-151-1/+1
* Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixe...Eli Friedman2011-10-141-0/+8
* Make sure that the register is in the register class before adding it as a ma...Bill Wendling2011-10-141-1/+3
* Mark the invoke call instruction as implicitly defining the callee-saved regi...Bill Wendling2011-10-141-2/+31
* Fix a non-firing assert. Change:Richard Trieu2011-10-141-1/+1
* A few 80-col violations.Evan Cheng2011-10-141-4/+8
* Add an implementation of the CanLowerReturn function to the PPC backendHal Finkel2011-10-142-0/+17
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