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* Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler2013-02-151-7/+10
* [mips] Disallow moving load/store instructions past volatile instructions.Akira Hatanaka2013-02-141-1/+1
* [mips] Replace usage of SmallSet with BitVector, which is used to keep track ofAkira Hatanaka2013-02-141-86/+83
* [mips] Fix comments and coding style violations. Declare functions to be const.Akira Hatanaka2013-02-141-64/+47
* The ARM NEON vector compare instructions take three arguments. However, the Joel Jones2013-02-141-0/+5
* The operand listing is very much outdated.Eli Bendersky2013-02-141-5/+2
* [mips] Simplify code in function Filler::findDelayInstr.Akira Hatanaka2013-02-141-38/+29
* Simplify code. Remove "else after return".Jakub Staszak2013-02-141-5/+4
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-145-259/+252
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-145-0/+54
* R600/SI: Fix int_SI_fs_interp_constantMichel Danzer2013-02-145-37/+34
* 80-colNadav Rotem2013-02-141-1/+2
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-141-74/+35
* Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao2013-02-142-6/+150
* R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune2013-02-142-1/+3
* R600: Export instructions are no longer terminatorVincent Lejeune2013-02-141-2/+2
* R600: Fold zero/one in export instructionsVincent Lejeune2013-02-143-80/+55
* R600: Do not fold modifier/litterals in vector instVincent Lejeune2013-02-141-2/+5
* AArch64: switch from neverHasSideEffects to hasSideEffects.Tim Northover2013-02-141-4/+4
* AArch64: stop claiming that NEON registers are usable for now.Tim Northover2013-02-141-11/+0
* AArch64: add block comments where missingTim Northover2013-02-1419-11/+86
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-141-4/+8
* Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky2013-02-141-3/+17
* R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer2013-02-141-1/+1
* Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola2013-02-142-1/+7
* Remove the form field from Mips16 instruction formats and set thingsReed Kotler2013-02-143-87/+73
* Don't assume the mangling of static functions.Rafael Espindola2013-02-141-6/+0
* Don't asume that a static function in an extern "C" block will not be mangled.Rafael Espindola2013-02-141-1/+1
* temporarily revert the patch due to some conflictsWeiming Zhao2013-02-132-150/+6
* Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta2013-02-131-0/+12
* R600: Add support for 128-bit parametersTom Stellard2013-02-132-0/+5
* Don't build tail calls to functions with three inreg arguments on x86-32 PIC.Nick Lewycky2013-02-131-5/+11
* Bug fix 13622: Add paired register support for inline asm with 64-bit data on...Weiming Zhao2013-02-132-6/+150
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-136-1052/+224
* [ms-inline-asm] Add support for memory references that have non-immediateChad Rosier2013-02-131-13/+18
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-133-3/+46
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+3
* Add registration for PPC-specific passes to allow the IR to be dumpedKrzysztof Parzyszek2013-02-133-3/+41
* X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer2013-02-131-0/+8
* Make jumptables work for -staticReed Kotler2013-02-131-0/+2
* Prevent insertion of "vzeroupper" before call that preserves YMM registers, s...Elena Demikhovsky2013-02-131-0/+10
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-131-1/+1
* Test commit. Fixed typo.David Peixotto2013-02-131-1/+1
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-20/+123
* [NVPTX] Disable vector registersJustin Holewinski2013-02-1217-1997/+1274
* R600: Fix regression with shadow array sampler on pre-SI GPUs.Michel Danzer2013-02-121-1/+1
* ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer2013-02-121-0/+33
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-121-1/+37
* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-4/+2
* [mips] Expand pseudo instructions before they are emitted inAkira Hatanaka2013-02-111-11/+38
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