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* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-284-14/+212
* ARM Allow 'q' registers in VLD/VST vector lists.Jim Grosbach2011-10-281-4/+47
* Remove the Alpha backend.Dan Gohman2011-10-2739-5315/+0
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ...Owen Anderson2011-10-271-0/+4
* Also set addrmode6 alignment when align==size.Jakob Stoklund Olesen2011-10-271-1/+1
* ARM isel for vld1, opcode selection for register stride post-index pseudos.Jim Grosbach2011-10-271-0/+4
* Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng2011-10-271-24/+43
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-272-3/+3
* Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.Jim Grosbach2011-10-271-0/+6
* Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.Jim Grosbach2011-10-271-1/+3
* A branch predicated on a constant can just FastEmit an unconditional branch.Chad Rosier2011-10-271-0/+6
* Rename NonScalarIntSafe to something more appropriate.Lang Hames2011-10-264-9/+9
* Add a TODO comment. FastISel works by parsing each basic block from the bottomChad Rosier2011-10-261-0/+1
* Factor a little more code into EmitCmp, which should have been done in the firstChad Rosier2011-10-261-23/+16
* Use EmitCmp in SelectBranch. No functional change intended.Chad Rosier2011-10-261-33/+6
* Factor out an EmitCmp function that can be used by both SelectCmp andChad Rosier2011-10-261-18/+24
* Thumb2 ldr pc-relative encoding fixes.Jim Grosbach2011-10-262-7/+16
* Fixes an issue reported by -verify-machineinstrs.Rafael Espindola2011-10-262-6/+7
* ARM parse parenthesized expressions for label references.Jim Grosbach2011-10-261-0/+1
* This commit introduces two fake instructions MORESTACK_RET andRafael Espindola2011-10-263-21/+39
* Make sure short memsets on ARM lower to stores, even when optimizing for size.Lang Hames2011-10-261-0/+2
* Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.Jim Grosbach2011-10-261-1/+1
* Revert r142530 at least temporarily while a discussion is had on llvm-commits...James Molloy2011-10-261-5/+2
* Use a worklist to prevent the iterator from becoming invalidated because of t...Bill Wendling2011-10-261-3/+4
* Revert part of r142530. The patch potentially hurts performance especiallyEvan Cheng2011-10-261-3/+3
* Corrects previously incorrect $sp change in MipsCompilationCallback.Bruno Cardoso Lopes2011-10-251-7/+7
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-253-17/+33
* Remove the Blackfin backend.Dan Gohman2011-10-2537-4415/+0
* Remove the SystemZ backend.Dan Gohman2011-10-2437-6279/+0
* Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.Jim Grosbach2011-10-243-4/+0
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-244-21/+33
* Don't crash on variable insertelement on ARM. PR10258.Eli Friedman2011-10-241-0/+11
* ARMConstantPoolMBB::print should print BB number.Evan Cheng2011-10-241-0/+1
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-242-0/+38
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-245-71/+181
* Add support to the old JIT for acquire/release loads and stores on x86. PR11...Eli Friedman2011-10-241-9/+24
* Fix a NEON disassembly case that was broken in the recent refactorings. As m...Owen Anderson2011-10-241-6/+0
* Change this overloaded use of Sched::Latency to be an overloadedDan Gohman2011-10-241-2/+2
* Remove the explicit request for "Latency" scheduling from MSP430,Dan Gohman2011-10-241-1/+0
* Thumb2 LDM instructions can target PC. Make sure to encode it.Jim Grosbach2011-10-241-8/+4
* Add X86 SARX, SHRX, and SHLX instructions.Craig Topper2011-10-231-18/+32
* Add X86 RORX instructionCraig Topper2011-10-235-0/+36
* Add X86 MULX instruction for disassembler.Craig Topper2011-10-231-0/+24
* Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 ...Craig Topper2011-10-221-5/+5
* Move various generated tables into read-only memory, fixing up const correctn...Benjamin Kramer2011-10-223-11/+12
* Fix pr11193.Nadav Rotem2011-10-221-3/+0
* The different flavors of ARM have different valid subsets of registers. CheckBill Wendling2011-10-221-3/+13
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-213-36/+18
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-214-30/+46
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-216-31/+38