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* Fix comment.Eric Christopher2010-10-171-1/+1
* Turn on AddOperator folding in GEP.Eric Christopher2010-10-171-1/+1
* Use the i12 immediate versions of the load instructions - they're handledEric Christopher2010-10-171-6/+6
* Add a MCObjectFormat class so that code common to all targets that use aRafael Espindola2010-10-162-4/+32
* X86-Windows: Emit an undefined global __fltused symbol when targeting WindowsMichael J. Spencer2010-10-161-0/+7
* Fix some funky formatting that got through.Eric Christopher2010-10-161-1/+3
* ARMCodeEmitter::emitMiscInstruction is dead. Long liveBill Wendling2010-10-151-45/+1
* Make sure offset is 0 for load/store register to the stack call.Eric Christopher2010-10-151-2/+2
* Formatting.Eric Christopher2010-10-151-4/+4
* Fix else if -> if in store machinery.Eric Christopher2010-10-151-1/+1
* Reformatting. No functionalogicality changes.Bill Wendling2010-10-151-19/+15
* Refactor ARM fast-isel reg + offset to be a base + offset.Eric Christopher2010-10-151-40/+45
* Encoding information for the various ARM saturating add/sub instructions.Jim Grosbach2010-10-151-46/+53
* ARM binary encoding information for RSB and RSC instructions.Jim Grosbach2010-10-151-44/+104
* Don't mark argument value stores as immutable, as otherwise the post-RAJim Grosbach2010-10-151-1/+1
* Use simple RegState::Define flag instead of getDefRegState(true).Bob Wilson2010-10-151-5/+5
* Expand GEP handling for constant offsets.Eric Christopher2010-10-151-23/+44
* When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomesJim Grosbach2010-10-151-2/+1
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-153-6/+35
* Remove unused ARMISD::AND selection DAG node.Bob Wilson2010-10-154-13/+0
* ARM instructions that are both predicated and set the condition codesBob Wilson2010-10-151-1/+1
* Encoding info for extension instructions.Jim Grosbach2010-10-151-0/+8
* Add missing Rd encoding for MOVs instruction.Jim Grosbach2010-10-141-0/+2
* Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudosJim Grosbach2010-10-142-9/+38
* Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'Jim Grosbach2010-10-143-6/+6
* MOVi16 and MOVT ARM mode encodings.Jim Grosbach2010-10-141-7/+19
* Simplify encoding information and add 'dst' operand info for TAILJMP.Jim Grosbach2010-10-141-8/+6
* Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. ItOscar Fuentes2010-10-141-5/+0
* Handle more complex GEP based loads and add a few TODOs to deal withEric Christopher2010-10-141-10/+50
* Add support for vmov.f64/.f32 encoding. There's a bit of a hack going onBill Wendling2010-10-142-14/+40
* Add encoding for 'fmstat'.Bill Wendling2010-10-142-4/+2
* - Add encodings for multiply add/subtract instructions in all their glory.Bill Wendling2010-10-142-67/+111
* Regenerate. No functional change, just cleanup.Jim Grosbach2010-10-141-6561/+6561
* Detabify and clean up 80 column violations.Jim Grosbach2010-10-133-40/+50
* A few 80 column fixes.Jim Grosbach2010-10-133-5/+5
* trailing whitespaceJim Grosbach2010-10-131-1/+1
* Add a FIXME.Jim Grosbach2010-10-131-0/+5
* Add operand encoding bits for SMC and SVC in ARM mode.Jim Grosbach2010-10-131-3/+7
* More encoding cleanup. Also add register Rd operands for indirect branches.Jim Grosbach2010-10-131-20/+20
* Simplify some ARM encoding information.Jim Grosbach2010-10-131-17/+4
* Update comment.Eric Christopher2010-10-131-1/+2
* Add a FIXME. The ADR instruction is a bit odd.Jim Grosbach2010-10-131-2/+6
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-135-19/+26
* Add MC encodings for VCVT* instrunctions.Bill Wendling2010-10-131-78/+157
* Add a FIXME.Jim Grosbach2010-10-131-0/+1
* Make a few more bits of some simple instructions explicit. nop, yield, wfe,Jim Grosbach2010-10-131-0/+15
* Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach2010-10-134-31/+64
* Fix encoding for compares. No Rd register.Jim Grosbach2010-10-131-6/+3
* Add ARM mode operand encoding information for ADDE/SUBE instructions.Jim Grosbach2010-10-131-19/+56
* Fix another case where we were preferring instructions with largeRafael Espindola2010-10-131-14/+18
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