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* Do not emit "generic" CPU string. This fixes PR4291.Anton Korobeynikov2009-06-011-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72696 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a grammaro and clarify a comment.Dan Gohman2009-05-311-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72668 91177308-0d34-0410-b5e6-96231b3b80d8
* First patch in the direction of splitting MachineCodeEmitter in two subclasses:Bruno Cardoso Lopes2009-05-3024-237/+551
| | | | | | | | JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
* (i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear ↵Evan Cheng2009-05-301-7/+0
| | | | | | the top 8 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72618 91177308-0d34-0410-b5e6-96231b3b80d8
* Untabification.Bill Wendling2009-05-3010-23/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
* Add placeholder for thumb2 stuffAnton Korobeynikov2009-05-295-20/+53
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
* More h-registers tricks: folding zext nodes.Evan Cheng2009-05-292-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72558 91177308-0d34-0410-b5e6-96231b3b80d8
* The MONITOR and MWAIT instructions have insufficient information forBill Wendling2009-05-283-10/+27
| | | | | | | | | | | | decoding. Essentially, they both map to the same column in the "opcode extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm complicates decoding this. Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code emitter special case these, a la [SML]FENCE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72556 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MOVMSKPDrr encoding.Evan Cheng2009-05-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72535 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PSIGND encoding bug. Patch by Sean Callanan.Evan Cheng2009-05-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72534 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit debug info for locals with proper scope.Sanjiv Gupta2009-05-285-70/+195
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72531 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the branch insns correctly.Sanjiv Gupta2009-05-281-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72529 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixing problems that got exposed after the refactoring of LegalizeDAG done ↵Sanjiv Gupta2009-05-281-4/+2
| | | | | | in 72447. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72521 91177308-0d34-0410-b5e6-96231b3b80d8
* Return the operand rather than a null SDValue when the given SELECT_CC Eli Friedman2009-05-281-3/+3
| | | | | | | | is actually legal. Part of LegalizeDAG cleanups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72513 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch brings the list of attributes in CPPBackend.cpp up to date with theJeffrey Yasskin2009-05-281-3/+8
| | | | | | | | list in Attributes.h. It also reorders the CPPBackend list to match so that it's easier to see that it's complete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72510 91177308-0d34-0410-b5e6-96231b3b80d8
* "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), butBill Wendling2009-05-282-2/+2
| | | | | | | | | | | the Intel manual (screenshot) says it should be 0b11110110 (f6). The existing encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be 0f e0." Patch by Sean Callanan! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72508 91177308-0d34-0410-b5e6-96231b3b80d8
* Added optimization that narrow load / op / store and the 'op' is a bit ↵Evan Cheng2009-05-282-0/+10
| | | | | | | | | | | | | | twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code. e.g. orl $65536, 8(%rax) => orb $1, 10(%rax) Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
* Ger rid of some dead code.Eli Friedman2009-05-272-36/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72494 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix sfence jit encoding. Patch by Sean Callanan.Evan Cheng2009-05-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72488 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for fround, fextend and FP_TO_SINTBruno Cardoso Lopes2009-05-279-29/+90
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and Eli Friedman2009-05-272-10/+13
| | | | | | | | | | FP_TO_XINT. Necessary for some cleanups I'm working on. Updated from the previous version (r72431) to fix a bug and make some things a bit clearer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72445 91177308-0d34-0410-b5e6-96231b3b80d8
* Back out r72431, it is causing a number of compilation crashes with clang.Daniel Dunbar2009-05-262-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72436 91177308-0d34-0410-b5e6-96231b3b80d8
* Update CPU capabilities for AMD machinesStefanus Du Toit2009-05-263-3/+31
| | | | | | | | | | | | | | | | | - added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and barcelona with appropriate sse3/4a levels - added FeatureSSE4A for amdfam10 processors in X86Subtarget: - added hasSSE4A - updated AutoDetectSubtargetFeatures to detect SSE4A - updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and family 10h as amdfam10 New processor names match those used by gcc. Patch by Paul Redmond! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP andEli Friedman2009-05-262-6/+6
| | | | | | | | FP_TO_XINT. Necessary for some cleanups I'm working on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72431 91177308-0d34-0410-b5e6-96231b3b80d8
* add some late optimizations that GCC does. It thinks these are a winChris Lattner2009-05-251-0/+14
| | | | | | | even on Core2, not just AMD processors which was a surprise to me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72396 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typoChris Lattner2009-05-251-1/+1
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* we should eventually add -march=atom and the new atom movbe instruction.Chris Lattner2009-05-251-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72387 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the PPC backend use a legal type for the operands to the BUILD_VECTOREli Friedman2009-05-241-5/+3
| | | | | | | | nodes it generates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72356 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the X86 backend mark EXTRACT_SUBVECTOR as Expand, at least for the Eli Friedman2009-05-231-0/+1
| | | | | | | | moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72350 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARMv7 architecture, Cortex processors and different FPU modes handling.Anton Korobeynikov2009-05-233-13/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit ARM Build AttributesAnton Korobeynikov2009-05-232-0/+91
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72336 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate CPU string out of SubtargetFeaturesAnton Korobeynikov2009-05-2312-18/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the x86 backend custom-lower UINT_TO_FP and FP_TO_UINT on 32-bit Eli Friedman2009-05-232-25/+64
| | | | | | | | | | | | | | | systems instead of attempting to promote them to a 64-bit SINT_TO_FP or FP_TO_SINT. This is in preparation for removing the type legalization code from LegalizeDAG: once type legalization is gone from LegalizeDAG, it won't be able to handle the i64 operand/result correctly. This isn't quite ideal, but I don't think any other operation for any target ends up in this situation, so treating this case specially seems reasonable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72324 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: Use libpthread in tblgen when needed. Updated list of sourceOscar Fuentes2009-05-221-0/+1
| | | | | | | files for PIC16 target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72277 91177308-0d34-0410-b5e6-96231b3b80d8
* Only 64-bit targets support TImode libcalls. Disable the TImode shift libcallsBob Wilson2009-05-221-0/+5
| | | | | | | for ARM. This fixes rdar://6908807. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72269 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit debug information for globals (which include automatic variables as ↵Sanjiv Gupta2009-05-224-0/+282
| | | | | | well because on PIC16 they are emitted as globals by the frontend). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72262 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor formatting fixes.Bob Wilson2009-05-201-2/+2
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* Try again. Allow call to immediate address for ELF or when in static ↵Evan Cheng2009-05-203-5/+18
| | | | | | relocation mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
* Cannot use immediate as call absolute target in PIC mode.Evan Cheng2009-05-201-1/+2
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* Fix pr4227: Handle large immediate values in inline assembly.Bob Wilson2009-05-191-1/+1
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* Follow up on new support for memory operands in ARM inline assembly.Bob Wilson2009-05-191-0/+4
| | | | | | | This fixes pr4233. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72115 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 andBob Wilson2009-05-191-1/+4
| | | | | | | the stack. Patch by Sandeep Patel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr4091: Add support for "m" constraint in ARM inline assembly.Bob Wilson2009-05-192-0/+34
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* Spacing fix.Dale Johannesen2009-05-191-1/+1
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* Add OpSize to 16-bit ADC and SBB.Dale Johannesen2009-05-181-14/+24
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* Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass hasBob Wilson2009-05-181-1/+4
| | | | | | | | | | to run last because it needs to know the exact size and position of every basic block. Currently CodePlacementOpt is set up to run last. It might be worthwhile to investigate reordering these passes, but for now, let's just make it work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72037 91177308-0d34-0410-b5e6-96231b3b80d8
* Fill in the missing patterns for ADC and SBB.Dale Johannesen2009-05-181-14/+97
| | | | | | | | Some comment cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72022 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark rotl/rotr as expand. This generates pretty ugly code, but this is ↵Anton Korobeynikov2009-05-171-0/+4
| | | | | | better than nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71976 91177308-0d34-0410-b5e6-96231b3b80d8
* TypoAnton Korobeynikov2009-05-172-3/+3
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* Fix a missing def-flag on a Mips epilogue load.Jakob Stoklund Olesen2009-05-161-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71935 91177308-0d34-0410-b5e6-96231b3b80d8
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