| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as cond... | Tom Stellard | 2012-07-16 | 1 | -8/+8 |
| * | Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonre... | Tom Stellard | 2012-07-16 | 1 | -1/+1 |
| * | Revert "Target/AMDGPU: Fix includes, or msvc build failed." | Tom Stellard | 2012-07-16 | 2 | -2/+2 |
| * | With r160248 in place this code is no longer needed. | Chad Rosier | 2012-07-16 | 2 | -17/+1 |
| * | Target/AMDGPU: Fix includes, or msvc build failed. | NAKAMURA Takumi | 2012-07-16 | 2 | -2/+2 |
| * | Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn fun... | NAKAMURA Takumi | 2012-07-16 | 1 | -1/+1 |
| * | Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional ... | NAKAMURA Takumi | 2012-07-16 | 1 | -8/+8 |
| * | Doubleword Shift Left Logical Plus 32 | Jack Carter | 2012-07-16 | 4 | -1/+57 |
| * | Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCom... | NAKAMURA Takumi | 2012-07-16 | 2 | -1/+3 |
| * | Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> ... | NAKAMURA Takumi | 2012-07-16 | 1 | -2/+2 |
| * | Build script changes for R600/SI Codegen v6 | Tom Stellard | 2012-07-16 | 1 | -1/+1 |
| * | AMDGPU: Add core backend files for R600/SI codegen v6 | Tom Stellard | 2012-07-16 | 114 | -0/+28329 |
| * | Fix a bug in the 3-address conversion of LEA when one of the operands is an | Nadav Rotem | 2012-07-16 | 1 | -0/+7 |
| * | This CL changes the function prologue and epilogue emitted on X86 when stack ... | Alexey Samsonov | 2012-07-16 | 1 | -53/+47 |
| * | Teach getTargetVShiftNode about TargetConstant nodes. | Nadav Rotem | 2012-07-15 | 1 | -1/+4 |
| * | Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention. | Nadav Rotem | 2012-07-15 | 2 | -3/+8 |
| * | AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit ve... | Nadav Rotem | 2012-07-14 | 1 | -1/+7 |
| * | This is one of the first steps at moving to replace target-dependent | Joel Jones | 2012-07-13 | 1 | -1/+1 |
| * | Remove variable_ops from call instructions in most targets. | Jakob Stoklund Olesen | 2012-07-13 | 11 | -46/+44 |
| * | Remove variable_ops from ARM call instructions. | Jakob Stoklund Olesen | 2012-07-13 | 3 | -22/+19 |
| * | The Mips specific relocation R_MIPS_GOT_DISP | Jack Carter | 2012-07-13 | 4 | -4/+12 |
| * | Make helper functions static. | Benjamin Kramer | 2012-07-13 | 1 | -1/+1 |
| * | Mark VINSERTI128rm as MayLoad=1. Fixes PR13348. | Craig Topper | 2012-07-13 | 1 | -2/+2 |
| * | Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and ... | Benjamin Kramer | 2012-07-12 | 2 | -4/+5 |
| * | Add intrinsics for Ivy Bridge's rdrand instruction. | Benjamin Kramer | 2012-07-12 | 3 | -3/+49 |
| * | Update GATHER instructions to support 2 read-write operands. Patch from mysel... | Craig Topper | 2012-07-12 | 4 | -16/+44 |
| * | ARM: fix typo in comments | Manman Ren | 2012-07-11 | 1 | -1/+1 |
| * | ARM: Fix optimizeCompare to correctly check safe condition. | Manman Ren | 2012-07-11 | 1 | -9/+14 |
| * | Patch for Mips direct object generation. | Jack Carter | 2012-07-11 | 1 | -0/+8 |
| * | This change removes an "initialization" warning. | Jack Carter | 2012-07-11 | 1 | -4/+3 |
| * | In register classes in MipsRegisterInfo.td, list the registers in ascending | Akira Hatanaka | 2012-07-11 | 1 | -99/+114 |
| * | [x86 fast-isel] Per discussion with Eric, add all cases to switch with verbose | Chad Rosier | 2012-07-11 | 1 | -1/+8 |
| * | X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair. | Manman Ren | 2012-07-11 | 1 | -1/+22 |
| * | Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. | Akira Hatanaka | 2012-07-11 | 2 | -3/+17 |
| * | [x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall back | Chad Rosier | 2012-07-11 | 1 | -1/+1 |
| * | When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, a... | Nadav Rotem | 2012-07-11 | 1 | -2/+12 |
| * | Lower RETURNADDR node in Mips backend. | Akira Hatanaka | 2012-07-11 | 3 | -5/+31 |
| * | Mips specific inline asm operand modifier 'L'. | Jack Carter | 2012-07-10 | 1 | -14/+22 |
| * | Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo to | Chad Rosier | 2012-07-10 | 2 | -4/+19 |
| * | Add support for dynamic stack realignment in the presence of dynamic allocas on | Chad Rosier | 2012-07-10 | 3 | -14/+106 |
| * | Improve the loading of load-anyext vectors by allowing the codegen to load | Nadav Rotem | 2012-07-10 | 1 | -27/+54 |
| * | Fix instruction description of VMOV (between two ARM core registers and two s... | Richard Barton | 2012-07-10 | 2 | -8/+8 |
| * | Reverse assembler/disassembler operand order for gather instructions. | Craig Topper | 2012-07-10 | 1 | -36/+11 |
| * | ARM: Allow more flexible patterns in NEON formats. | Jim Grosbach | 2012-07-10 | 1 | -53/+53 |
| * | Make register Mips::RA allocatable if not in mips16 mode. | Akira Hatanaka | 2012-07-10 | 9 | -37/+88 |
| * | Revert r159938 (and r159945) to appease the buildbots. | Chad Rosier | 2012-07-09 | 2 | -8/+8 |
| * | X86: implement functions to analyze & synthesize CMOV|SET|Jcc | Manman Ren | 2012-07-09 | 1 | -138/+185 |
| * | Reapply r158846. | Akira Hatanaka | 2012-07-09 | 1 | -114/+77 |
| * | Some formatting to keep Clang happy | Richard Barton | 2012-07-09 | 1 | -4/+4 |
| * | Oops - correct broken disassembly for VMOV | Richard Barton | 2012-07-09 | 1 | -1/+1 |
