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* "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), butBill Wendling2009-05-282-2/+2
| | | | | | | | | | | the Intel manual (screenshot) says it should be 0b11110110 (f6). The existing encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be 0f e0." Patch by Sean Callanan! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72508 91177308-0d34-0410-b5e6-96231b3b80d8
* Added optimization that narrow load / op / store and the 'op' is a bit ↵Evan Cheng2009-05-282-0/+10
| | | | | | | | | | | | | | twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code. e.g. orl $65536, 8(%rax) => orb $1, 10(%rax) Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
* Ger rid of some dead code.Eli Friedman2009-05-272-36/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72494 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix sfence jit encoding. Patch by Sean Callanan.Evan Cheng2009-05-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72488 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for fround, fextend and FP_TO_SINTBruno Cardoso Lopes2009-05-279-29/+90
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and Eli Friedman2009-05-272-10/+13
| | | | | | | | | | FP_TO_XINT. Necessary for some cleanups I'm working on. Updated from the previous version (r72431) to fix a bug and make some things a bit clearer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72445 91177308-0d34-0410-b5e6-96231b3b80d8
* Back out r72431, it is causing a number of compilation crashes with clang.Daniel Dunbar2009-05-262-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72436 91177308-0d34-0410-b5e6-96231b3b80d8
* Update CPU capabilities for AMD machinesStefanus Du Toit2009-05-263-3/+31
| | | | | | | | | | | | | | | | | - added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and barcelona with appropriate sse3/4a levels - added FeatureSSE4A for amdfam10 processors in X86Subtarget: - added hasSSE4A - updated AutoDetectSubtargetFeatures to detect SSE4A - updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and family 10h as amdfam10 New processor names match those used by gcc. Patch by Paul Redmond! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP andEli Friedman2009-05-262-6/+6
| | | | | | | | FP_TO_XINT. Necessary for some cleanups I'm working on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72431 91177308-0d34-0410-b5e6-96231b3b80d8
* add some late optimizations that GCC does. It thinks these are a winChris Lattner2009-05-251-0/+14
| | | | | | | even on Core2, not just AMD processors which was a surprise to me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72396 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typoChris Lattner2009-05-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72395 91177308-0d34-0410-b5e6-96231b3b80d8
* we should eventually add -march=atom and the new atom movbe instruction.Chris Lattner2009-05-251-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72387 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the PPC backend use a legal type for the operands to the BUILD_VECTOREli Friedman2009-05-241-5/+3
| | | | | | | | nodes it generates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72356 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the X86 backend mark EXTRACT_SUBVECTOR as Expand, at least for the Eli Friedman2009-05-231-0/+1
| | | | | | | | moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72350 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARMv7 architecture, Cortex processors and different FPU modes handling.Anton Korobeynikov2009-05-233-13/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit ARM Build AttributesAnton Korobeynikov2009-05-232-0/+91
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72336 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate CPU string out of SubtargetFeaturesAnton Korobeynikov2009-05-2312-18/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the x86 backend custom-lower UINT_TO_FP and FP_TO_UINT on 32-bit Eli Friedman2009-05-232-25/+64
| | | | | | | | | | | | | | | systems instead of attempting to promote them to a 64-bit SINT_TO_FP or FP_TO_SINT. This is in preparation for removing the type legalization code from LegalizeDAG: once type legalization is gone from LegalizeDAG, it won't be able to handle the i64 operand/result correctly. This isn't quite ideal, but I don't think any other operation for any target ends up in this situation, so treating this case specially seems reasonable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72324 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: Use libpthread in tblgen when needed. Updated list of sourceOscar Fuentes2009-05-221-0/+1
| | | | | | | files for PIC16 target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72277 91177308-0d34-0410-b5e6-96231b3b80d8
* Only 64-bit targets support TImode libcalls. Disable the TImode shift libcallsBob Wilson2009-05-221-0/+5
| | | | | | | for ARM. This fixes rdar://6908807. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72269 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit debug information for globals (which include automatic variables as ↵Sanjiv Gupta2009-05-224-0/+282
| | | | | | well because on PIC16 they are emitted as globals by the frontend). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72262 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor formatting fixes.Bob Wilson2009-05-201-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72172 91177308-0d34-0410-b5e6-96231b3b80d8
* Try again. Allow call to immediate address for ELF or when in static ↵Evan Cheng2009-05-203-5/+18
| | | | | | relocation mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
* Cannot use immediate as call absolute target in PIC mode.Evan Cheng2009-05-201-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72154 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr4227: Handle large immediate values in inline assembly.Bob Wilson2009-05-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72138 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow up on new support for memory operands in ARM inline assembly.Bob Wilson2009-05-191-0/+4
| | | | | | | This fixes pr4233. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72115 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 andBob Wilson2009-05-191-1/+4
| | | | | | | the stack. Patch by Sandeep Patel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr4091: Add support for "m" constraint in ARM inline assembly.Bob Wilson2009-05-192-0/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
* Spacing fix.Dale Johannesen2009-05-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72083 91177308-0d34-0410-b5e6-96231b3b80d8
* Add OpSize to 16-bit ADC and SBB.Dale Johannesen2009-05-181-14/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72045 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass hasBob Wilson2009-05-181-1/+4
| | | | | | | | | | to run last because it needs to know the exact size and position of every basic block. Currently CodePlacementOpt is set up to run last. It might be worthwhile to investigate reordering these passes, but for now, let's just make it work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72037 91177308-0d34-0410-b5e6-96231b3b80d8
* Fill in the missing patterns for ADC and SBB.Dale Johannesen2009-05-181-14/+97
| | | | | | | | Some comment cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72022 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark rotl/rotr as expand. This generates pretty ugly code, but this is ↵Anton Korobeynikov2009-05-171-0/+4
| | | | | | better than nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71976 91177308-0d34-0410-b5e6-96231b3b80d8
* TypoAnton Korobeynikov2009-05-172-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71975 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a missing def-flag on a Mips epilogue load.Jakob Stoklund Olesen2009-05-161-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71935 91177308-0d34-0410-b5e6-96231b3b80d8
* Remember to set def-flag on register loaded from stack slot in CellSPU.Jakob Stoklund Olesen2009-05-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71934 91177308-0d34-0410-b5e6-96231b3b80d8
* Reflow to fit 80-col.Mike Stump2009-05-141-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71813 91177308-0d34-0410-b5e6-96231b3b80d8
* Reflow to fit 80-col.Mike Stump2009-05-141-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71812 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the names of the exception handling sjlj instrinsics toJim Grosbach2009-05-144-14/+16
| | | | | | | | | | | llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html. (llvm.eh.sjlj.longjmp documentation coming when that implementation is added). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71758 91177308-0d34-0410-b5e6-96231b3b80d8
* Spelling correction s/builting/builtin/ and remove trailing whitespace in a ↵Jim Grosbach2009-05-131-10/+10
| | | | | | few places git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71735 91177308-0d34-0410-b5e6-96231b3b80d8
* Run code placement optimization for targets that want it (arm and x86 for now).Evan Cheng2009-05-132-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71726 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-1318-150/+193
| | | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
* Run through the list of globals once and sectionize all types of globlas ↵Sanjiv Gupta2009-05-134-38/+72
| | | | | | includeing declarations. Later emit them from their section lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71661 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an int64_t variant of abs, for host environmentsDale Johannesen2009-05-131-2/+2
| | | | | | | | | | | | | without one. Use it where we were using abs on int64_t objects. (I strongly suspect the casts to unsigned in the fragments in LoopStrengthReduce are not doing whatever the original intent was, but the obvious change to uint64_t doesn't work. Maybe later.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71612 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for GCC compatible builtin setjmp and longjmp intrinsics. This isJim Grosbach2009-05-124-4/+52
| | | | | | | | | a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but rather used by the front-end as target hooks for exception handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71610 91177308-0d34-0410-b5e6-96231b3b80d8
* correct register class for tADDspi to GPR since the register will always be SPJim Grosbach2009-05-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71602 91177308-0d34-0410-b5e6-96231b3b80d8
* More MSVC fixes -- class/struct conflicts.Bill Wendling2009-05-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71601 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 col violations.Evan Cheng2009-05-121-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71582 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up a few minor typos in comments.Bob Wilson2009-05-121-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71563 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 80-col violations and remove trailing whitespace. No functional changes.Bob Wilson2009-05-121-69/+71
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71562 91177308-0d34-0410-b5e6-96231b3b80d8
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