| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete C... | Eli Friedman | 2012-11-17 | 1 | -0/+1 |
| * | Initial implementation of MipsTargetLowering::isLegalAddressingMode. | Akira Hatanaka | 2012-11-17 | 2 | -0/+22 |
| * | Rename methods like PairSRegs() to createSRegpairNode() to meet our coding | Weiming Zhao | 2012-11-17 | 1 | -40/+34 |
| * | Remove hard coded registers in ARM ldrexd and strexd instructions | Weiming Zhao | 2012-11-16 | 6 | -62/+185 |
| * | Make sure FABS on v2f32 and v4f32 is legal on ARM NEON | Anton Korobeynikov | 2012-11-16 | 2 | -7/+9 |
| * | Fix handling of aliases to functions. | Richard Osborne | 2012-11-16 | 1 | -13/+9 |
| * | [NVPTX] Order global variables in def-use order before emiting them in the fi... | Justin Holewinski | 2012-11-16 | 1 | -3/+67 |
| * | Using const cast to alleviate a warning. | Joe Abbey | 2012-11-16 | 1 | -1/+2 |
| * | Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris. | Duncan Sands | 2012-11-16 | 3 | -5/+63 |
| * | Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of ve... | Craig Topper | 2012-11-16 | 2 | -0/+68 |
| * | [mips] Fix delay slot filler so that instructions with register operand $1 are | Akira Hatanaka | 2012-11-16 | 1 | -17/+34 |
| * | Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing | Eli Friedman | 2012-11-15 | 1 | -0/+2 |
| * | [mips] Add predicate HasFPIdx for floating-point indexed load instruction | Akira Hatanaka | 2012-11-15 | 6 | -11/+16 |
| * | PowerPC: Lowering floor intrinsic for Altivec | Adhemerval Zanella | 2012-11-15 | 2 | -0/+14 |
| * | Add assertions in MipsLongBranch which check the size of basic blocks. | Akira Hatanaka | 2012-11-15 | 1 | -1/+7 |
| * | Return 0 instead of false. | Jakub Staszak | 2012-11-15 | 1 | -3/+3 |
| * | Simplify code. | Jakub Staszak | 2012-11-15 | 1 | -1/+1 |
| * | Use empty parens for empty function parameter list instead of '(void)'. | Dmitri Gribenko | 2012-11-15 | 3 | -3/+3 |
| * | Revert changing FNEG of v4f32 to Expand. It's legal. | Craig Topper | 2012-11-15 | 1 | -1/+0 |
| * | Make FNEG and FABS of v4f32 Expand. | Craig Topper | 2012-11-15 | 1 | -0/+2 |
| * | Make a bunch of floating point operations on vectors Expand so that instructi... | Craig Topper | 2012-11-15 | 1 | -6/+10 |
| * | Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics. | Craig Topper | 2012-11-15 | 3 | -1/+13 |
| * | Remove unneeded #includes. | Jakub Staszak | 2012-11-14 | 1 | -3/+0 |
| * | NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable] | NAKAMURA Takumi | 2012-11-14 | 1 | -6/+4 |
| * | Remove the CellSPU port. | Eric Christopher | 2012-11-14 | 52 | -14677/+1 |
| * | Fix invalid asserts, use llvm_unreachable instead. | Jakub Staszak | 2012-11-14 | 1 | -3/+3 |
| * | Added multiclass for post-increment load instructions. | Jyotsna Verma | 2012-11-14 | 4 | -233/+187 |
| * | X86: Enable SSE memory intrinsics even when stack alignment is less than 16 b... | Benjamin Kramer | 2012-11-14 | 1 | -7/+2 |
| * | The code pattern "imm0_255_neg" is used for checking if an immediate value is... | Nadav Rotem | 2012-11-14 | 1 | -6/+7 |
| * | [NVPTX] Implement custom lowering of loads/stores for i1 | Justin Holewinski | 2012-11-14 | 2 | -2/+61 |
| * | X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches. | Jim Grosbach | 2012-11-14 | 2 | -9/+42 |
| * | Set FFLOOR of vectors to expand to keep intruction selection from failing. | Craig Topper | 2012-11-14 | 1 | -0/+1 |
| * | Factor out an overly replicated typecast. No functional change. | Craig Topper | 2012-11-14 | 1 | -65/+66 |
| * | Set FFLOOR for vectors to expand on CellSPU to keep instruction selection fro... | Craig Topper | 2012-11-14 | 1 | -1/+2 |
| * | Use TARGET2 relocation for TType references on ARM. | Anton Korobeynikov | 2012-11-14 | 5 | -20/+38 |
| * | Add (some) PowerPC TLS relocation types to ELF.h and | Ulrich Weigand | 2012-11-13 | 1 | -2/+18 |
| * | Fix wrong PowerPC instruction opcodes for: | Ulrich Weigand | 2012-11-13 | 2 | -4/+4 |
| * | Fix wrong PowerPC instruction encodings due to | Ulrich Weigand | 2012-11-13 | 2 | -10/+10 |
| * | Fix instruction encoding for "bd(n)z" on PowerPC, | Ulrich Weigand | 2012-11-13 | 3 | -14/+15 |
| * | Fix instruction encoding for "isel" on PowerPC, | Ulrich Weigand | 2012-11-13 | 3 | -2/+22 |
| * | X86: when constructing VZEXT_LOAD from other loads, makes sure its output | Manman Ren | 2012-11-13 | 1 | -0/+12 |
| * | misched: Allow subtargets to enable misched and dependent options. | Andrew Trick | 2012-11-13 | 1 | -0/+4 |
| * | Test commit. | Jyotsna Verma | 2012-11-13 | 1 | -0/+1 |
| * | misched: Target-independent support for load/store clustering. | Andrew Trick | 2012-11-12 | 1 | -0/+6 |
| * | Make TOC order deterministic by using MapVector instead of DenseMap. | Ulrich Weigand | 2012-11-12 | 1 | -3/+3 |
| * | Remove unused field. | Eric Christopher | 2012-11-12 | 1 | -1/+0 |
| * | Fix PR14314 | Michael Liao | 2012-11-12 | 1 | -2/+2 |
| * | [NVPTX] Add more precise PTX/SM target attributes | Justin Holewinski | 2012-11-12 | 4 | -11/+57 |
| * | Move some helper methods to being static functions in the implementation file. | Craig Topper | 2012-11-11 | 2 | -20/+7 |
| * | Use the isTruncFree and isZExtFree API to figure out of these operations are ... | Nadav Rotem | 2012-11-11 | 1 | -2/+10 |
