| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [PowerPC] Use multiclass to generate extended branch mnemonics | Ulrich Weigand | 2013-06-10 | 1 | -51/+22 |
| * | Silencing an MSVC warning about comparing signed and unsigned values. | Aaron Ballman | 2013-06-10 | 1 | -1/+1 |
| * | Fix misleading comments in ARMAsmParser | Amaury de la Vieuville | 2013-06-10 | 1 | -6/+6 |
| * | ARM: ISB cannot be passed the same options as DMB | Amaury de la Vieuville | 2013-06-10 | 7 | -2/+157 |
| * | [NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore... | Justin Holewinski | 2013-06-10 | 3 | -39/+11 |
| * | Fix a regression I introduced when I expanded the complex pseudos in | Reed Kotler | 2013-06-09 | 2 | -9/+10 |
| * | Fix ARM unwind opcode assembler in several cases. | Logan Chien | 2013-06-09 | 3 | -169/+185 |
| * | Removed PackedDouble domain from scalar instructions. Added more formats for ... | Elena Demikhovsky | 2013-06-09 | 2 | -43/+60 |
| * | ARM FastISel fix load register classes | JF Bastien | 2013-06-09 | 1 | -4/+4 |
| * | [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc bac... | Venkatraman Govindaraju | 2013-06-08 | 7 | -162/+61 |
| * | ARM: fix VMOVvnf32 decoding when ambiguous with VCVT | Amaury de la Vieuville | 2013-06-08 | 1 | -0/+4 |
| * | ARM: enforce SRS decoding constraints | Amaury de la Vieuville | 2013-06-08 | 1 | -1/+7 |
| * | ARM: fix CPS decoding when ambiguous with QADD | Amaury de la Vieuville | 2013-06-08 | 2 | -0/+34 |
| * | ARM: fix VCVT decoding | Amaury de la Vieuville | 2013-06-08 | 1 | -2/+2 |
| * | Fix unused variable warning from my previous patch. | JF Bastien | 2013-06-08 | 1 | -0/+1 |
| * | [mips] Use a helper function which compares the size of the source and | Akira Hatanaka | 2013-06-08 | 2 | -8/+21 |
| * | R600: Use a refined heuristic to choose when switching clause | Vincent Lejeune | 2013-06-07 | 2 | -10/+47 |
| * | R600: Anti dep better handled in tex clause | Vincent Lejeune | 2013-06-07 | 1 | -6/+4 |
| * | Remember the anyext patterns. | Jakob Stoklund Olesen | 2013-06-07 | 1 | -0/+2 |
| * | Add missing zextloadi1 to i64 patterns. PR16721. | Jakob Stoklund Olesen | 2013-06-07 | 1 | -0/+3 |
| * | Disallow i64 div/rem in PPC32 counter loops | Hal Finkel | 2013-06-07 | 1 | -0/+7 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 3 | -6/+6 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 7 | -16/+33 |
| * | Remove unused c'tor. | Bill Wendling | 2013-06-07 | 1 | -7/+2 |
| * | R600: Fix calculation of stack offset in AMDGPUFrameLowering | Tom Stellard | 2013-06-07 | 1 | -21/+2 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 4 | -8/+10 |
| * | R600: Rework subtarget info and remove AMDILDevice classes | Tom Stellard | 2013-06-07 | 36 | -1458/+218 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 4 | -9/+10 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 21 | -63/+75 |
| * | R600: Fix the fetch limits for R600 generation GPUs | Tom Stellard | 2013-06-07 | 4 | -27/+30 |
| * | R600: Move Subtarget feature definitions into AMDGPU.td | Tom Stellard | 2013-06-07 | 2 | -64/+66 |
| * | R600: Remove unnecessary include | Tom Stellard | 2013-06-07 | 3 | -2/+4 |
| * | ARM FastISel integer sext/zext improvements | JF Bastien | 2013-06-07 | 1 | -38/+103 |
| * | R600: Don't compare iterators of different maps. | Benjamin Kramer | 2013-06-07 | 1 | -1/+1 |
| * | Vincent says the element is at most once in the vector, so we don't need a fu... | Benjamin Kramer | 2013-06-07 | 1 | -3/+7 |
| * | Fix a typo in asm string of BP* family of instructions. With this fix | Roman Divacky | 2013-06-07 | 1 | -1/+1 |
| * | R600: Fix a potential iterator invalidation issue. | Benjamin Kramer | 2013-06-07 | 1 | -5/+3 |
| * | R600: Remove an extra break in R600OptimizeVectorRegisters.cpp | Vincent Lejeune | 2013-06-07 | 1 | -3/+1 |
| * | Fold variable that's only used in assert into the assert. | Benjamin Kramer | 2013-06-07 | 1 | -2/+1 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 7 | -20/+27 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 11 | -40/+67 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 3 | -6/+5 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 4 | -10/+6 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 9 | -19/+25 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 15 | -42/+48 |
| * | Don't cache the instruction info and register info objects. | Bill Wendling | 2013-06-07 | 6 | -28/+22 |
| * | ARM sched model: Use the right resources for DIV | Arnold Schwaighofer | 2013-06-07 | 1 | -1/+1 |
| * | ARM sched model: Add VFP div instruction on Swift | Arnold Schwaighofer | 2013-06-07 | 1 | -0/+16 |
| * | ARM sched model: Add SIMD/VFP load/store instructions on Swift | Arnold Schwaighofer | 2013-06-07 | 1 | -0/+364 |
| * | [Sparc]: Use cmp instruction instead of subcc to compare integers. | Venkatraman Govindaraju | 2013-06-07 | 3 | -17/+19 |
