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* Fix one more encoding bug.Nate Begeman2008-05-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51057 91177308-0d34-0410-b5e6-96231b3b80d8
* - Don't treat anyext 16-bit load as a 32-bit load if it's volatile.Evan Cheng2008-05-131-2/+2
| | | | | | | - Correct a pasto. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51054 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding files for Microchip's PIC16 target.Sanjiv Gupta2008-05-1323-0/+3323
| | | | | | | | | | | | | | | | | | | A brief description about PIC16: =============================== PIC16 is an 8-bit microcontroller with only one 8-bit register which is the accumulator. All arithmetic/load/store operations are 8-bit only. The architecture has two address spaces: program and data. The program memory is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory. It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register). Two classes of registers exist: (8-bit class which is only one accumulator) (16-bit class, which contains one or more 16 bit pointer(s)) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51027 91177308-0d34-0410-b5e6-96231b3b80d8
* Instead of a vector load, shuffle and then extract an element. Load the ↵Evan Cheng2008-05-132-50/+1
| | | | | | | | | | | | element from address with an offset. pshufd $1, (%rdi), %xmm0 movd %xmm0, %eax => movl 4(%rdi), %eax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51026 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix and encoding error in the psrad xmm, imm8 instruction.Nate Begeman2008-05-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51020 91177308-0d34-0410-b5e6-96231b3b80d8
* On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for ↵Evan Cheng2008-05-132-27/+28
| | | | | | i8 anyext load to i16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51019 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the use of static and anonymous namespaces. This turned upDan Gohman2008-05-1315-159/+155
| | | | | | | | several things that were neither in an anonymous namespace nor static but not intended to be global. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach Legalize how to scalarize VSETCCNate Begeman2008-05-121-0/+27
| | | | | | | Teach X86 a few more vsetcc patterns. Custom lowering for unsupported ones is next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51009 91177308-0d34-0410-b5e6-96231b3b80d8
* Xform bitconvert(build_pair(load a, load b)) to a single load if the load ↵Evan Cheng2008-05-122-73/+5
| | | | | | locations are at the right offset from each other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51008 91177308-0d34-0410-b5e6-96231b3b80d8
* Constify the machine instruction passed into theBill Wendling2008-05-122-2/+3
| | | | | | | "is{Trivially,Really}ReMaterializable" methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial X86 codegen support for VSETCC.Nate Begeman2008-05-123-11/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a copy+paste bug; pseudo-instructions shouldn't haveDan Gohman2008-05-121-21/+14
| | | | | | | encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50997 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can ↵Evan Cheng2008-05-122-67/+27
| | | | | | make use of it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50991 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for vicmp/vfcmp codegen, more legalize support coming.Nate Begeman2008-05-121-0/+1
| | | | | | | This is necessary to unbreak the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50988 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a compile error on compilers that still want a return valueDan Gohman2008-05-121-0/+1
| | | | | | | in a non-void function that calls abort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50969 91177308-0d34-0410-b5e6-96231b3b80d8
* Add noteAnton Korobeynikov2008-05-111-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50959 91177308-0d34-0410-b5e6-96231b3b80d8
* When transforming a vector_shuffle to a load, the base address must not be ↵Evan Cheng2008-05-101-0/+2
| | | | | | an undef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50940 91177308-0d34-0410-b5e6-96231b3b80d8
* For now, abort when an ISD::VAARG is encountered on x86-64, ratherDan Gohman2008-05-102-3/+18
| | | | | | | | | | than silently generate invalid code. llvm-gcc does not currently use VAArgInst; it lowers va_arg in the front-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50930 91177308-0d34-0410-b5e6-96231b3b80d8
* Some clean up.Evan Cheng2008-05-101-16/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50929 91177308-0d34-0410-b5e6-96231b3b80d8
* If movl top bits are undef, let it be selected to movlps, etc.Evan Cheng2008-05-101-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50928 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a pattern to do move the low element of a v4f32 and zero extend the rest.Evan Cheng2008-05-091-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50922 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle a few more cases of folding load i64 into xmm and zero top bits.Evan Cheng2008-05-095-29/+90
| | | | | | | Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
* Use movq to move low half of XMM register and zero-extend the rest.Evan Cheng2008-05-081-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50874 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle vector move / load which zero the destination register top bits (i.e. ↵Evan Cheng2008-05-085-144/+158
| | | | | | movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
* Output correct exception handling and frame infoDuncan Sands2008-05-072-3/+0
| | | | | | | | | | | | | | | | | | | on x86-64 linux. This causes no regressions on 32 bit linux and 32 bit ppc. More tests pass on 64 bit ppc with no regressions. I didn't turn on eh on 64 bit linux because the intrinsics needed to compile the eh runtime aren't done yet. But if you turn it on and link with the mainline runtime then eh seems to work fine on x86-64 linux with this patch. Thanks to Dale for testing. The main point of the patch is that if you output that some object is encoded using 4 bytes you had better not output 8 bytes for it: the patch makes everything consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50825 91177308-0d34-0410-b5e6-96231b3b80d8
* Match things like 'armv5tejl-unknown-linux-gnu' for PR2290Chris Lattner2008-05-061-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50698 91177308-0d34-0410-b5e6-96231b3b80d8
* Make several variable declarations static.Dan Gohman2008-05-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50696 91177308-0d34-0410-b5e6-96231b3b80d8
* add a micro optzn.Chris Lattner2008-05-051-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50681 91177308-0d34-0410-b5e6-96231b3b80d8
* Improved generated code for atomic operatorsMon P Wang2008-05-051-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50677 91177308-0d34-0410-b5e6-96231b3b80d8
* Code clean up. No functionality change.Evan Cheng2008-05-051-20/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50675 91177308-0d34-0410-b5e6-96231b3b80d8
* Added addition atomic instrinsics and, or, xor, min, and max.Mon P Wang2008-05-055-10/+308
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix IsLinux being uninitialized on non-Linux targets.Dan Gohman2008-05-051-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50660 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 80col violationAnton Korobeynikov2008-05-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50654 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a dedicated IsLinux flag instead of an ELFLinux TargetType.Dan Gohman2008-05-053-10/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50649 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AsmPrinter support for emitting a directive to declare thatDan Gohman2008-05-054-2/+18
| | | | | | | | | | the code being generated does not require an executable stack. Also, add target-specific code to make use of this on Linux on x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
* Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look ↵Anton Korobeynikov2008-05-044-16/+62
| | | | | | | | | for tlsaddr pattern), but should work. Work is in progress, more models will follow git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50630 91177308-0d34-0410-b5e6-96231b3b80d8
* Select vector shift with non-immediate i32 shift amount operand by first ↵Evan Cheng2008-05-041-1/+90
| | | | | | moving the operand into the right register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
* Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This ↵Evan Cheng2008-05-032-72/+44
| | | | | | allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
* Undo r50574. We are already ensuring the folded load address is 16-byte aligned.Evan Cheng2008-05-021-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50578 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 column violation.Evan Cheng2008-05-021-6/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50575 91177308-0d34-0410-b5e6-96231b3b80d8
* Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 ↵Evan Cheng2008-05-021-8/+0
| | | | | | value but the load folding variant expects a 16-byte aligned address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50574 91177308-0d34-0410-b5e6-96231b3b80d8
* Tail call optimization improvements:Arnold Schwaighofer2008-04-3011-288/+847
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
* Bug fixes and updates for CellSPU, syncing up with trunk. Most notableScott Michel2008-04-307-53/+133
| | | | | | | | | fixes are target-specific lowering of frame indices, fix constants generated for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor- TargetNode(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50462 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't do stupid things: doInitialization(Module&) is not applicable to ↵Anton Korobeynikov2008-04-291-17/+2
| | | | | | ModulePass :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50433 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the SVOffset values for loads and stores produced byDan Gohman2008-04-284-16/+18
| | | | | | | | memcpy/memset expansion. It was a bug for the SVOffset value to be used in the actual address calculations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix FP return for Win64 ABIAnton Korobeynikov2008-04-281-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50342 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly lower vararg's FORMAL_ARGUMENTS node on win64Anton Korobeynikov2008-04-271-14/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50325 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle fp80 for win64Anton Korobeynikov2008-04-271-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50324 91177308-0d34-0410-b5e6-96231b3b80d8
* A few inline asm cleanups:Chris Lattner2008-04-264-15/+15
| | | | | | | | | | - Make targetlowering.h fit in 80 cols. - Make LowerAsmOperandForConstraint const. - Make lowerXConstraint -> LowerXConstraint - Make LowerXConstraint return a const char* instead of taking a string byref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
* no need to implement this method and just have it callChris Lattner2008-04-262-14/+0
| | | | | | | the default impl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50311 91177308-0d34-0410-b5e6-96231b3b80d8
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