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* Fix Alpha test and support for private linkage.Rafael Espindola2009-01-151-1/+2
* Expand insert/extract of a <4 x i32> with a variable index.Mon P Wang2009-01-151-2/+10
* Add the private linkage.Rafael Espindola2009-01-1519-51/+68
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-1510-10/+10
* Add load-folding table entries for BT*ri8 instructions.Dan Gohman2009-01-151-0/+3
* Make getWidenVectorType const.Dan Gohman2009-01-152-2/+2
* Const-qualify getPreIndexedAddressParts and friends.Dan Gohman2009-01-154-14/+15
* Don't fold address calculations which use negative offsets intoRichard Osborne2009-01-151-2/+2
* Update the operands used when building LDAWSP instructions to match the .tdRichard Osborne2009-01-152-2/+1
* - Convert remaining i64 custom lowering into custom instruction emissionScott Michel2009-01-157-185/+333
* Add pseudo instructions to the XCore for (load|store|load address) of aRichard Osborne2009-01-143-77/+66
* fix memleaksNuno Lopes2009-01-131-0/+2
* BT appears to be available on all >= i386 chips.Dan Gohman2009-01-131-1/+0
* Don't use a BT instruction if the AND has multiple uses.Dan Gohman2009-01-131-1/+3
* Disable the register+memory forms of the bt instructions for now. ThanksDan Gohman2009-01-132-12/+20
* Add bt instructions that take immediate operands.Dan Gohman2009-01-132-2/+32
* Fix a few more JIT encoding issues in the BT instructions.Dan Gohman2009-01-131-2/+2
* Checking in conditionals, function call, arrays and libcalls implementation.Sanjiv Gupta2009-01-1312-275/+1149
* make -march=cpp handle the nocapture attribute, make it assert if itChris Lattner2009-01-131-22/+19
* Use DebugInfo interface to lower dbg_* intrinsics.Devang Patel2009-01-133-5/+8
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-1223-44/+45
* 80 col violation.Evan Cheng2009-01-101-1/+2
* Removed trailing whitespace from Makefiles.Misha Brukman2009-01-0918-38/+38
* Add load-folding table entries for MOVDQA.Dan Gohman2009-01-091-0/+6
* Whitespace and other minor adjustments to make SSE instructions haveDan Gohman2009-01-091-26/+32
* Convert DwarfWriter into a pass.Devang Patel2009-01-086-57/+62
* add some more crazy strlen and memcpy stuff I noticed in spec.Chris Lattner2009-01-081-0/+99
* add some notes about strlen craziness in eon.Chris Lattner2009-01-081-0/+57
* Fix off-by-one error in traversing an array; this fixes a test.Misha Brukman2009-01-071-1/+1
* Add patterns to match conditional moves with loads foldedDan Gohman2009-01-072-1/+101
* Add load-folding table entries for cmovno too.Dan Gohman2009-01-071-0/+3
* Define instructions for cmovo and cmovno.Dan Gohman2009-01-073-9/+90
* X86_COND_C and X86_COND_NC are alternate mnemonics forDan Gohman2009-01-075-66/+29
* Revert r42653 and forward-port the code that lets INC64_32r beDan Gohman2009-01-061-2/+4
* CellSPU:Scott Michel2009-01-067-61/+38
* CellSPU: Update the READMEScott Michel2009-01-061-7/+18
* CellSPU:Scott Michel2009-01-066-57/+213
* Revert r61415 and r61484. Duncan was correct that these weren't needed.Bill Wendling2009-01-052-4/+0
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-0520-27/+13
* squash warnings.Devang Patel2009-01-055-1/+6
* Atom and Core i7 do not have same model number after all.Evan Cheng2009-01-051-4/+3
* CellSPU:Scott Michel2009-01-051-1/+111
* CellSPU:Scott Michel2009-01-053-35/+82
* Add Intel processors core i7 and atom.Evan Cheng2009-01-032-1/+4
* Fix PR3210: Detect more Intel processors. Patch by Torok Edwin.Evan Cheng2009-01-031-2/+15
* CellSPU:Scott Michel2009-01-033-109/+122
* - Make copyRegToReg use the "LR" assembler synonym for "OR". Makes findingScott Michel2009-01-021-38/+50
* Do not isel load folding bt instructions for pentium m, core, core2, and AMD ...Evan Cheng2009-01-024-29/+51
* Fix x86 CPU id detection to identify Penryn (and future processors).Evan Cheng2009-01-021-2/+11
* Use movaps / movd to extract vector element 0 even with sse4.1. It's still ch...Evan Cheng2009-01-021-0/+8
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