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* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-203-31/+14
* X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, ...NAKAMURA Takumi2011-07-201-1/+2
* Don't leak CodeGenInfos.Benjamin Kramer2011-07-201-1/+3
* Change name of class.Akira Hatanaka2011-07-201-23/+23
* Define classes for definitions of atomic instructions.Akira Hatanaka2011-07-201-106/+42
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-193-2/+28
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-193-8/+19
* ARM assembly parsing of MRS instruction.Jim Grosbach2011-07-192-7/+11
* Enhance the FixedLengthDecoder to be able to generate plausible-looking decod...Owen Anderson2011-07-191-2/+11
* Change variable name.Akira Hatanaka2011-07-191-3/+3
* ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.Jim Grosbach2011-07-192-9/+8
* Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL orAkira Hatanaka2011-07-191-13/+14
* Use descriptive variable names. Akira Hatanaka2011-07-191-154/+177
* ARM assembly parsing for MOV (register).Jim Grosbach2011-07-191-19/+21
* Tidy up.Jim Grosbach2011-07-191-12/+8
* Tighten conditional for 'mov' cc_out.Jim Grosbach2011-07-191-1/+2
* ARM assembly parsing for MOV (immediate).Jim Grosbach2011-07-193-16/+63
* Remove unused code.Jim Grosbach2011-07-191-54/+3
* Fix comments.Akira Hatanaka2011-07-191-10/+10
* Remove redundant instructions.Akira Hatanaka2011-07-191-16/+12
* Separate code that modifies control flow from code that adds instruction to Akira Hatanaka2011-07-191-18/+18
* ARM range checking for so_imm operands in assembly parsing.Jim Grosbach2011-07-192-0/+15
* Convert gep_type_begin and gep_type_end to use ArrayRef.Jay Foad2011-07-191-1/+1
* Convert TargetData::getIndexedOffset to use ArrayRef.Jay Foad2011-07-191-4/+5
* Add intrinsics for the zext / sext instructions.Richard Osborne2011-07-191-7/+13
* Add intrinsics for the testct, testwct instructions.Richard Osborne2011-07-191-1/+9
* Add intrinsics for the peek and endin instructions.Richard Osborne2011-07-191-1/+8
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-1946-273/+371
* Make EmitAtomic functions return the correct MachineBasicBlocks so thatAkira Hatanaka2011-07-191-22/+28
* Do not insert instructions in reverse order.Akira Hatanaka2011-07-191-14/+16
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple...Owen Anderson2011-07-183-12/+40
* Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of theEvan Cheng2011-07-181-3/+0
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-1829-93/+78
* Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause ...Owen Anderson2011-07-181-1/+1
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-1846-432/+341
* Do not treat atomic.load.sub differently than other atomic binary intrinsics.Akira Hatanaka2011-07-181-12/+2
* Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from Akira Hatanaka2011-07-183-85/+23
* Re-apply r135319 with a fix for the constant island pass.Owen Anderson2011-07-183-48/+29
* Be more smart with VCVTSS2SD. Also place the patterns close to theBruno Cardoso Lopes2011-07-181-20/+10
* Add AVX 128-bit sqrt versionsBruno Cardoso Lopes2011-07-181-0/+11
* Change destination register operands of SC instructions so that uniqueAkira Hatanaka2011-07-181-8/+13
* Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previ...Frits van Bommel2011-07-182-14/+14
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-1836-231/+231
* Revert r135319 in an attempt to get to unbreak testers.Owen Anderson2011-07-162-27/+48
* Add AVX 128-bit patterns for sint_to_fpBruno Cardoso Lopes2011-07-161-0/+20
* Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tB...Owen Anderson2011-07-152-48/+27
* Fix a couple of things:Bruno Cardoso Lopes2011-07-151-61/+52
* Add a few patterns for 256-bit bitcasts. No testcases now, they areBruno Cardoso Lopes2011-07-151-0/+9
* PR10370: Make sure we know how to relax push correctly on x86-64.Eli Friedman2011-07-151-0/+3
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ...Owen Anderson2011-07-155-19/+14