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* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-203-31/+14
| | | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, ↵NAKAMURA Takumi2011-07-201-1/+2
| | | | | | to appease test/CodeGen/X86 on cygwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't leak CodeGenInfos.Benjamin Kramer2011-07-201-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135555 91177308-0d34-0410-b5e6-96231b3b80d8
* Change name of class.Akira Hatanaka2011-07-201-23/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135550 91177308-0d34-0410-b5e6-96231b3b80d8
* Define classes for definitions of atomic instructions.Akira Hatanaka2011-07-201-106/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135546 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-193-2/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-193-8/+19
| | | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing of MRS instruction.Jim Grosbach2011-07-192-7/+11
| | | | | | | | | Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance the FixedLengthDecoder to be able to generate plausible-looking ↵Owen Anderson2011-07-191-2/+11
| | | | | | decoders for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
* Change variable name.Akira Hatanaka2011-07-191-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135522 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.Jim Grosbach2011-07-192-9/+8
| | | | | | | Add range checking to the immediate operands. Update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL orAkira Hatanaka2011-07-191-13/+14
| | | | | | | ANDi, when the instruction does not have any immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
* Use descriptive variable names. Akira Hatanaka2011-07-191-154/+177
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135514 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for MOV (register).Jim Grosbach2011-07-191-19/+21
| | | | | | | | | Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2011-07-191-12/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135507 91177308-0d34-0410-b5e6-96231b3b80d8
* Tighten conditional for 'mov' cc_out.Jim Grosbach2011-07-191-1/+2
| | | | | | | | Make sure we only clobber the cc_out operand if it is indeed a default non-setting operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135506 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for MOV (immediate).Jim Grosbach2011-07-193-16/+63
| | | | | | | | | Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused code.Jim Grosbach2011-07-191-54/+3
| | | | | | | cc_out and pred operands are added during parsing via custom C++ now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135497 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comments.Akira Hatanaka2011-07-191-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135496 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove redundant instructions.Akira Hatanaka2011-07-191-16/+12
| | | | | | | | | | - In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate code that modifies control flow from code that adds instruction to Akira Hatanaka2011-07-191-18/+18
| | | | | | | | basic blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135490 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM range checking for so_imm operands in assembly parsing.Jim Grosbach2011-07-192-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135489 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert gep_type_begin and gep_type_end to use ArrayRef.Jay Foad2011-07-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135481 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert TargetData::getIndexedOffset to use ArrayRef.Jay Foad2011-07-191-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135478 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the zext / sext instructions.Richard Osborne2011-07-191-7/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the testct, testwct instructions.Richard Osborne2011-07-191-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135475 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the peek and endin instructions.Richard Osborne2011-07-191-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135474 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-1946-273/+371
| | | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
* Make EmitAtomic functions return the correct MachineBasicBlocks so thatAkira Hatanaka2011-07-191-22/+28
| | | | | | | | | ExpandISelPseudos::runOnMachineFunction does not visit instructions that have just been added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135465 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not insert instructions in reverse order.Akira Hatanaka2011-07-191-14/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135464 91177308-0d34-0410-b5e6-96231b3b80d8
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having ↵Owen Anderson2011-07-183-12/+40
| | | | | | multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135442 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of theEvan Cheng2011-07-181-3/+0
| | | | | | | use of TargetFrameLowering in TargetAsmInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135439 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-1829-93/+78
| | | | | | | better location welcome). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause ↵Owen Anderson2011-07-181-1/+1
| | | | | | decoding conflicts in the new-style disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135434 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-1846-432/+341
| | | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not treat atomic.load.sub differently than other atomic binary intrinsics.Akira Hatanaka2011-07-181-12/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135418 91177308-0d34-0410-b5e6-96231b3b80d8
* Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from Akira Hatanaka2011-07-183-85/+23
| | | | | | | | | moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135415 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply r135319 with a fix for the constant island pass.Owen Anderson2011-07-183-48/+29
| | | | | | | Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135414 91177308-0d34-0410-b5e6-96231b3b80d8
* Be more smart with VCVTSS2SD. Also place the patterns close to theBruno Cardoso Lopes2011-07-181-20/+10
| | | | | | definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135407 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 128-bit sqrt versionsBruno Cardoso Lopes2011-07-181-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135404 91177308-0d34-0410-b5e6-96231b3b80d8
* Change destination register operands of SC instructions so that uniqueAkira Hatanaka2011-07-181-8/+13
| | | | | | | virtual registers are used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135403 91177308-0d34-0410-b5e6-96231b3b80d8
* Migrate LLVM and Clang to use the new makeArrayRef(...) functions where ↵Frits van Bommel2011-07-182-14/+14
| | | | | | | | | previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-1836-231/+231
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r135319 in an attempt to get to unbreak testers.Owen Anderson2011-07-162-27/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135343 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 128-bit patterns for sint_to_fpBruno Cardoso Lopes2011-07-161-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135332 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and ↵Owen Anderson2011-07-152-48/+27
| | | | | | tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135319 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of things:Bruno Cardoso Lopes2011-07-151-61/+52
| | | | | | | | | | | | | | | | | | | | | | | | 1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us canonize the loads and handle things the same way we use to handle for 128-bit registers. Despite of what one of the removed comments explained, the load promotion would not mess with VPERM, it's only a matter of doing the appropriate bitcasts when this instructions comes to be introduced. Also make LOAD v8i32 legal. 2) Doing 1) exposed two bugs: - v4i64 was being promoted to itself for several opcodes (introduced in r124447 by David Greene) causing endless recursion and the stack to explode. - there was no support for allOnes BUILD_VECTORs and ANDNP would fail to match because it was generating early target constant pools during lowering. 3) The testcases are already checked-in, doing 1) exposed the bugs in the current testcases. 4) Tidy up code to be more clear and explicit about AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135313 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few patterns for 256-bit bitcasts. No testcases now, they areBruno Cardoso Lopes2011-07-151-0/+9
| | | | | | comming together with other tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135312 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10370: Make sure we know how to relax push correctly on x86-64.Eli Friedman2011-07-151-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135303 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-155-19/+14
| | | | | | to simplify the path towards an auto-generated disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
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