external_llvm.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	Hexagon: Use multiclass for Jump instructions.	Jyotsna Verma	2013-05-01	14	-263/+336
*	Hexagon: Clear isKill flag on the predicate register in	Jyotsna Verma	2013-05-01	1	-1/+5
*	This patch breaks up Wrap.h so that it does not have to include all of	Filip Pizlo	2013-05-01	2	-2/+1
*	Put VMOVPQIto64rr in the VRPDI class.	Rafael Espindola	2013-05-01	1	-3/+3
*	[mips] Fix handling of instructions which copy to/from accumulator registers.	Akira Hatanaka	2013-04-30	7	-37/+43
*	[mips] Instruction selection patterns for DSP-ASE vector select and compare	Akira Hatanaka	2013-04-30	5	-3/+145
*	[mips] Simplify code.	Akira Hatanaka	2013-04-30	1	-4/+1
*	[mips] Clear isCommutable bit of instructions which are not commutable.	Akira Hatanaka	2013-04-30	1	-14/+8
*	Text files should not be marked executable.	Rafael Espindola	2013-04-30	1	-0/+0
*	s tightens up the encoding description for ARM post-indexed ldr instructions....	Mihai Popa	2013-04-30	1	-0/+1
*	Refactoring patch.	Stepan Dyatkovskiy	2013-04-30	5	-66/+100
*	R600: Always use texture cache for compute shaders	Vincent Lejeune	2013-04-30	1	-2/+6
*	R600: use native for alu	Vincent Lejeune	2013-04-30	4	-4/+135
*	R600: Packetize instructions	Vincent Lejeune	2013-04-30	6	-3/+464
*	R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips	Vincent Lejeune	2013-04-30	5	-32/+105
*	R600: Add a Bank Swizzle operand	Vincent Lejeune	2013-04-30	4	-11/+19
*	R600: Take inner dependency into tex/vtx clauses	Vincent Lejeune	2013-04-30	1	-0/+34
*	R600: Turn TEX/VTX into native instructions	Vincent Lejeune	2013-04-30	3	-15/+50
*	R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions	Vincent Lejeune	2013-04-30	9	-58/+95
*	R600: Add some new processor variants	Vincent Lejeune	2013-04-30	2	-1/+3
*	R600: Clean up instruction class definitions	Vincent Lejeune	2013-04-30	1	-23/+14
*	R600: config section now reports use of killgt	Vincent Lejeune	2013-04-30	1	-0/+4
*	R600: Use correct CF_END instruction on Northern Island GPUs	Tom Stellard	2013-04-29	1	-1/+1
*	R600: Fix encoding of CF_END_{EG, R600} instructions	Tom Stellard	2013-04-29	1	-0/+1
*	AArch64 InstrFormats:	Jia Liu	2013-04-28	1	-1/+1
*	Make all darwin ppc stubs local.	Rafael Espindola	2013-04-27	1	-1/+9
*	R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE	Tom Stellard	2013-04-26	1	-0/+2
*	ARM: Fix encoding of hint instruction for Thumb.	Quentin Colombet	2013-04-26	4	-16/+22
*	PowerPC: Use RegisterOperand instead of RegisterClass operands	Ulrich Weigand	2013-04-26	3	-432/+452
*	PowerPC: Fix encoding of vsubcuw and vsum4sbs instructions	Ulrich Weigand	2013-04-26	1	-2/+2
*	PowerPC: Fix encoding of stfsu and stfdu instructions	Ulrich Weigand	2013-04-26	1	-2/+2
*	PowerPC: Fix encoding of rldimi and rldcl instructions	Ulrich Weigand	2013-04-26	3	-3/+36
*	PowerPC: Support PC-relative fixup_ppc_brcond14.	Ulrich Weigand	2013-04-26	1	-0/+3
*	ARM/NEON: Pattern match vector integer abs to vabs.	Benjamin Kramer	2013-04-26	1	-0/+23
*	X86: Now that we have a canonical form for vector integer abs, match it into ...	Benjamin Kramer	2013-04-26	1	-0/+51
*	Mips assembler: .set reorder support	Jack Carter	2013-04-25	1	-0/+13
*	Make function documentation conform to llvm standards.	Preston Gurd	2013-04-25	1	-30/+32
*	ARM cost model: Integer div and rem is lowered to a function call	Arnold Schwaighofer	2013-04-25	1	-0/+68
*	This patch adds the X86FixupLEAs pass, which will reduce instruction	Preston Gurd	2013-04-25	7	-0/+270
*	Fix section relocation for SECTIONREL32 with immediate offset.	Rafael Espindola	2013-04-25	1	-2/+15
*	[mips] Add definitions of micromips load and store instructions.	Akira Hatanaka	2013-04-25	4	-17/+43
*	[mips] Add definitions of micromips shift instructions.	Akira Hatanaka	2013-04-25	4	-12/+62
*	R600: Initialize BooleanVectorContents	Tom Stellard	2013-04-24	1	-0/+1
*	R600: Use SHT_PROGBITS for the .AMDGPU.config section	Tom Stellard	2013-04-24	1	-1/+1
*	Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.	Jyotsna Verma	2013-04-23	2	-176/+149
*	Hexagon: Define relations for GP-relative instructions.	Jyotsna Verma	2013-04-23	1	-15/+17
*	Add more tests for r179925 to verify correct handling of signext/zeroext; str...	Stephen Lin	2013-04-23	1	-3/+6
*	Lowercase "is" boolean variable prefix for consistency within function, no fu...	Stephen Lin	2013-04-23	1	-12/+12
*	Hexagon: Remove assembler mapped instruction definitions.	Jyotsna Verma	2013-04-23	5	-108/+80
*	Change commentary for PowerPC Boolean vector contents.	Bill Schmidt	2013-04-23	1	-1/+2