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* [SystemZ] Extend 32-bit RISBG optimizations to high wordsRichard Sandiford2013-10-011-8/+16
* [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high wordsRichard Sandiford2013-10-012-6/+22
* ARM: support interrupt attributeTim Northover2013-10-018-21/+148
* [SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and aboveRichard Sandiford2013-10-011-7/+18
* [SystemZ] Allow integer AND involving high wordsRichard Sandiford2013-10-015-63/+107
* [SystemZ] Allow integer XOR involving high wordsRichard Sandiford2013-10-014-5/+15
* Remove several unused variables.Rafael Espindola2013-10-012-4/+0
* [SystemZ] Allow integer OR involving high wordsRichard Sandiford2013-10-014-13/+41
* [SystemZ] Allow integer insertions with a high-word destinationRichard Sandiford2013-10-014-2/+43
* [SystemZ] Allow selects with a high-word destinationRichard Sandiford2013-10-012-2/+4
* [SystemZ] Add patterns to load a constant into a high word (IIHF)Richard Sandiford2013-10-017-5/+59
* [ARM] Remove an unused function from the disassembler.Joey Gouly2013-10-011-11/+0
* Test commit. Updated comment.Matheus Almeida2013-10-011-1/+1
* [SystemZ] Add register zero extensions involving at least one high wordRichard Sandiford2013-10-013-2/+29
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-015-29/+22
* [SystemZ] Add truncating high-word stores (STCH and STHH)Richard Sandiford2013-10-012-4/+24
* [SystemZ] Add zero-extending high-word loads (LLCH and LLHH)Richard Sandiford2013-10-012-2/+22
* [SystemZ] Add sign-extending high-word loads (LBH and LHH)Richard Sandiford2013-10-012-2/+22
* [SystemZ] Use upper words of GR64s for codegenRichard Sandiford2013-10-0110-13/+184
* [SystemZ] Reapply: Add definitions of LFH and STFHRichard Sandiford2013-10-011-0/+4
* [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intr...Daniel Sanders2013-10-012-9/+23
* This patch adds aliases for Mips sub instruction with immediate operands. Cor...Vladimir Medic2013-10-012-2/+38
* AVX-512: Added X86vzmovl patternsElena Demikhovsky2013-10-011-0/+5
* Remove 0 as a valid encoding for the m-mmmm field.Craig Topper2013-10-011-2/+0
* Remove unneeded fields from disassembler internal instruction format.Craig Topper2013-10-012-20/+0
* BEXTR should be defined to take same type for bother operands.Craig Topper2013-10-011-1/+1
* Forgot to add a break statement.Preston Gurd2013-09-301-0/+1
* The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddressPreston Gurd2013-09-301-0/+8
* [mips][msa] Direct Object Emission for I8 instructions.Jack Carter2013-09-302-28/+39
* [mips][msa] Direct Object Emission for I5 instructions.Jack Carter2013-09-302-49/+64
* [ARM] Clean up ARMAsmParser::validateInstruction().Tilmann Scheller2013-09-301-38/+36
* [mips][msa] Direct Object Emission for 2R instructions.Jack Carter2013-09-302-16/+21
* [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPRJack Carter2013-09-302-15/+26
* [ARM] Assembler: ARM LDRD with writeback requires the base register to be dif...Tilmann Scheller2013-09-301-4/+19
* Swift model: Fix uop description on some writesArnold Schwaighofer2013-09-301-2/+11
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-304-0/+26
* [SystemZ] Revert r191661: Add definitions of LFH and STFHRichard Sandiford2013-09-301-4/+0
* [SystemZ] Add definitions of LFH and STFHRichard Sandiford2013-09-301-0/+4
* [SystemZ] Add GRH32 for the high word of a GR64Richard Sandiford2013-09-306-14/+38
* [SystemZ] Rename subregs and add subreg_h32Richard Sandiford2013-09-309-60/+61
* [SystemZ] Add change missing from previous commitRichard Sandiford2013-09-301-1/+1
* [SystemZ] Rename 32-bit GPR registersRichard Sandiford2013-09-306-20/+20
* Various x86 disassembler fixes.Craig Topper2013-09-303-47/+12
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ca...Craig Topper2013-09-292-14/+8
* Add comments for XOPA map introduced with TBM instructions.aCraig Topper2013-09-292-2/+4
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-288-12/+12
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-282-3/+3
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-283-44/+40
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-281-4/+12
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-282-76/+58
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