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* [mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selectsAkira Hatanaka2013-04-112-64/+4
* [mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.Akira Hatanaka2013-04-113-13/+12
* Optimize vector select from all 0s or all 1sMichael Liao2013-04-111-0/+45
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-115-34/+56
* Enhance bool simplifcation in X86 to handle more casesMichael Liao2013-04-111-6/+35
* R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-04-111-0/+1
* Whitespace.NAKAMURA Takumi2013-04-111-2/+1
* Make PPCInstrInfo::isPredicated always return falseHal Finkel2013-04-111-16/+8
* MC: Support COFF image-relative MCSymbolRefsNico Rieck2013-04-101-2/+16
* fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo2013-04-101-3/+3
* fixed to disassemble with tab after mnemonic rather than spaceKay Tiong Khoo2013-04-101-2/+2
* In the X86 back end, getMemoryOperandNo() returns the offsetPreston Gurd2013-04-102-12/+22
* Tidy up, fix and simplify a few of the SMLocs. Prior to r179109 the Start SMLocChad Rosier2013-04-101-11/+13
* Remove unused variable.Chad Rosier2013-04-101-1/+0
* PPC: Don't predicate a diamond with two counter decrementsHal Finkel2013-04-102-3/+24
* Reapply r179115, but use parsePrimaryExpression a little more judiciously.Chad Rosier2013-04-101-3/+3
* R600/SI: Add pattern for AMDGPUurecipMichel Danzer2013-04-103-3/+13
* This is for an experimental option -mips-os16. The idea is to compile allReed Kotler2013-04-106-1/+185
* R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addrVincent Lejeune2013-04-101-1/+10
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-105-7/+22
* R600/SI: dynamical figure out the reg class of MIMGChristian Konig2013-04-106-2/+63
* R600/SI: adjust writemask to only the used componentsChristian Konig2013-04-104-2/+91
* R600/SI: remove image sample writemaskChristian Konig2013-04-102-14/+13
* Cleanup PPCInstrInfo::DefinesPredicateHal Finkel2013-04-101-5/+10
* PPC: Prep for if conversion of bctr[l]Hal Finkel2013-04-103-2/+37
* __sincosf_stret returns sinf / cosf in bits 0:31 and 32:63 of xmm0, not inEvan Cheng2013-04-101-5/+19
* Mips specific inline asm operand modifier 'D' Jack Carter2013-04-091-3/+9
* Allow PPC B and BLR to be if-converted into some predicated formsHal Finkel2013-04-095-0/+208
* Cleanup. No functional change intended.Chad Rosier2013-04-091-5/+5
* Cleanup. No functional change intended.Chad Rosier2013-04-091-16/+16
* Revert r179115 as it looks to have killed the ASan tests.Chad Rosier2013-04-091-5/+5
* This patch enables llvm to switch between compiling for mips32/mips64 Reed Kotler2013-04-0915-11/+333
* [ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need toChad Rosier2013-04-091-5/+5
* Cleanup PPCEarlyReturnHal Finkel2013-04-091-28/+31
* [ms-inline asm] Maintain a StringRef to reference a symbol in a parsed operand,Chad Rosier2013-04-091-24/+38
* Use virtual base registers on PPCHal Finkel2013-04-092-15/+164
* Extract a function.Jakob Stoklund Olesen2013-04-091-31/+17
* Compute correct frame sizes for SPARC v9 64-bit frames.Jakob Stoklund Olesen2013-04-093-25/+40
* X86 cost model: Model cost for uitofp and sitofp on SSE2Arnold Schwaighofer2013-04-081-3/+34
* [ms-inline asm] Add support for ImmDisp [ Symbol ] memory operands.Chad Rosier2013-04-081-12/+6
* Generate PPC early conditional returnsHal Finkel2013-04-086-24/+160
* R600: Control Flow support for pre EG genVincent Lejeune2013-04-083-72/+240
* AArch64: remove barriers from AArch64 atomic operations.Tim Northover2013-04-083-145/+193
* ARM: Remove unused variable.Benjamin Kramer2013-04-081-2/+0
* Cleanup and improve PPC fsel generationHal Finkel2013-04-071-7/+33
* Implement LowerCall_64 for the SPARC v9 64-bit ABI.Jakob Stoklund Olesen2013-04-072-0/+228
* PPC rotate instructions don't have unmodeled side effctsHal Finkel2013-04-072-3/+6
* Most PPC M[TF]CR instructions do not have side effectsHal Finkel2013-04-072-5/+19
* PPC pre-increment load instructions do not have side effectsHal Finkel2013-04-071-2/+3
* PPC pre-increment load instructions do not have side effectsHal Finkel2013-04-072-3/+3
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