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* Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.Eli Friedman2011-12-091-4/+3
* Revert r146184. I am seeing performance regression cause by this patch in one...Devang Patel2011-12-081-10/+11
* ARM convenience aliases for VSQRT.Jim Grosbach2011-12-082-1/+7
* Support/FileSystem: Implement recursive_directory_iterator and makeMichael J. Spencer2011-12-082-9/+11
* Fix infinite loop in DSE when deleting a free in a reachable loop that's alsoNick Lewycky2011-12-081-1/+1
* Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417Evan Cheng2011-12-081-0/+21
* ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.Jim Grosbach2011-12-081-1/+1
* Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can...Owen Anderson2011-12-084-16/+56
* ARM VSHR implied destination operand form aliases.Jim Grosbach2011-12-083-0/+77
* Add various missing AVX patterns which was causing crashes. Sadly, the generatedEvan Cheng2011-12-081-0/+32
* Refactor. No intentional functionality change.Devang Patel2011-12-081-29/+41
* Add rather verbose stats for fast-isel failures.Chad Rosier2011-12-081-0/+153
* ARM asm parser, just issue a warning for a duplicate reg in a list.Jim Grosbach2011-12-081-1/+7
* Filter "sink to" candidate blocks sooner. This avoids unnecessary computation...Devang Patel2011-12-081-11/+13
* Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo inAkira Hatanaka2011-12-081-4/+11
* ARM VSUB implied destination operand form aliases.Jim Grosbach2011-12-081-0/+24
* Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don'...Owen Anderson2011-12-081-11/+0
* ARM VQADD implied destination operand form aliases.Jim Grosbach2011-12-081-0/+35
* ARM a few more VMUL implied destination operand form aliases.Jim Grosbach2011-12-081-0/+18
* Implement 64-bit support for thread local storage handling.Akira Hatanaka2011-12-085-55/+51
* Teach SelectionDAG to match more calls to libm functions onto existing SDNode...Owen Anderson2011-12-084-10/+79
* ARM assembler support for register name aliases.Jim Grosbach2011-12-081-2/+16
* Make MachineInstr instruction property queries more flexible. This change allEvan Cheng2011-12-081-5/+5
* Many of the SSE patterns should not be selected when AVX is available. This l...Evan Cheng2011-12-084-4/+11
* Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsicsDaniel Dunbar2011-12-081-22/+0
* Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this a...Jan Sjödin2011-12-082-14/+11
* Fix a bug in the integer-promotion of bitcast operations on vector types.Nadav Rotem2011-12-081-1/+1
* Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for...Stepan Dyatkovskiy2011-12-081-0/+22
* MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (anot...Hal Finkel2011-12-081-1/+1
* Reverting r145899 as it breaks clang self-hostingPete Cooper2011-12-081-0/+66
* ARM NEON two-operand aliases for VSHL(immediate).Jim Grosbach2011-12-083-0/+35
* Drop the HasInlineAsm flag.Jakob Stoklund Olesen2011-12-081-8/+2
* ARM NEON two-operand aliases for VSHL(register).Jim Grosbach2011-12-081-0/+35
* Simplify offset verification.Jakob Stoklund Olesen2011-12-081-9/+4
* Fix copy/past-o.Jim Grosbach2011-12-081-2/+2
* ARM NEON two-operand aliases for VMUL.Jim Grosbach2011-12-081-0/+5
* Don't include alignment padding in BBInfo.Size.Jakob Stoklund Olesen2011-12-081-145/+86
* ARM VFP support 'fmrs/fmsr' aliases for 'vldr'Jim Grosbach2011-12-082-0/+3
* ARM VFP support 'flds/fldd' aliases for 'vldr'Jim Grosbach2011-12-082-1/+7
* ARM optional destination operand variants for VEXT instructions.Jim Grosbach2011-12-081-0/+17
* Fix 80-column.Chad Rosier2011-12-081-10/+11
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-083-10/+56
* Fix comments.Chad Rosier2011-12-081-0/+1
* EngineBuilder: support for custom TargetOptions. Fixes thePeter Collingbourne2011-12-072-2/+5
* Fix comments.Chad Rosier2011-12-071-2/+2
* ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.Jim Grosbach2011-12-071-1/+3
* Modify class ReadHardware and add definition of 64-bit version of instructionAkira Hatanaka2011-12-072-3/+6
* Add newline.Akira Hatanaka2011-12-071-1/+2
* Add 64-bit HWR29 register.Akira Hatanaka2011-12-071-0/+2
* 32 to 64-bit anyext pattern.Akira Hatanaka2011-12-071-0/+4
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