| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add cmake bits for md5. | Eric Christopher | 2013-05-21 | 1 | -0/+1 |
| * | Add an md5 library derived from a public domain implementation for dwarf4 | Eric Christopher | 2013-05-21 | 1 | -0/+266 |
| * | Dwarf: use a single line table to generate assembly when .loc is used. | Manman Ren | 2013-05-21 | 1 | -3/+14 |
| * | Add some additional functions to the list of helper functions for | Reed Kotler | 2013-05-21 | 1 | -2/+13 |
| * | PR14606: Debug Info for namespace aliases/DW_TAG_imported_module | David Blaikie | 2013-05-20 | 3 | -11/+44 |
| * | The DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase... | Bill Wendling | 2013-05-20 | 2 | -5/+5 |
| * | No need to store the TargetMachine variable in this class. | Bill Wendling | 2013-05-20 | 1 | -4/+2 |
| * | Remove unused #include. | Bill Wendling | 2013-05-20 | 1 | -1/+0 |
| * | Rename LoopSimplify.h to LoopUtils.h | Hal Finkel | 2013-05-20 | 2 | -2/+2 |
| * | [mips] Add (setne $lhs, 0) instruction selection pattern. | Akira Hatanaka | 2013-05-20 | 1 | -0/+2 |
| * | [mips] Trap on integer division by zero. | Akira Hatanaka | 2013-05-20 | 4 | -5/+58 |
| * | Remove copied preheader insertion logic from PPCCTRLoops | Hal Finkel | 2013-05-20 | 1 | -85/+3 |
| * | Expose InsertPreheaderForLoop from LoopSimplify to other passes | Hal Finkel | 2013-05-20 | 1 | -11/+12 |
| * | [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a s... | Justin Holewinski | 2013-05-20 | 1 | -9/+7 |
| * | [NVPTX] Add programmatic interface to NVVMReflect pass | Justin Holewinski | 2013-05-20 | 2 | -3/+24 |
| * | Rename PPC MTCTRse to MTCTRloop | Hal Finkel | 2013-05-20 | 3 | -7/+7 |
| * | Add a PPCCTRLoops verification pass | Hal Finkel | 2013-05-20 | 3 | -0/+164 |
| * | R600: Fix bug detected by GCC warning. | Benjamin Kramer | 2013-05-20 | 1 | -2/+2 |
| * | R600/SI: Use a multiclass for MUBUF_Load_Helper | Tom Stellard | 2013-05-20 | 2 | -20/+30 |
| * | R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions | Tom Stellard | 2013-05-20 | 1 | -0/+1 |
| * | R600/SI: Add pattern for rotr | Tom Stellard | 2013-05-20 | 1 | -0/+2 |
| * | R600: Swap the legality of rotl and rotr | Tom Stellard | 2013-05-20 | 7 | -28/+11 |
| * | R600/SI: Add patterns for 64-bit shift operations | Tom Stellard | 2013-05-20 | 2 | -3/+22 |
| * | R600/SI: Use the same names for VOP3 operands and encoding fields | Tom Stellard | 2013-05-20 | 2 | -37/+37 |
| * | R600/SI: Make fitsRegClass() operands const | Tom Stellard | 2013-05-20 | 2 | -2/+3 |
| * | VSTn instructions have a number of encoding constraints which are not impleme... | Mihai Popa | 2013-05-20 | 2 | -21/+72 |
| * | Q registers are encoded in fields of the same length as D registers. As Q reg... | Mihai Popa | 2013-05-20 | 1 | -1/+1 |
| * | [SystemZ] Add long branch pass | Richard Sandiford | 2013-05-20 | 11 | -34/+399 |
| * | [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs | Justin Holewinski | 2013-05-20 | 7 | -80/+525 |
| * | [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need... | Justin Holewinski | 2013-05-20 | 1 | -2/+12 |
| * | PR15868 fix. | Stepan Dyatkovskiy | 2013-05-20 | 5 | -11/+69 |
| * | Also expand 64-bit bitcasts. | Jakob Stoklund Olesen | 2013-05-20 | 1 | -0/+2 |
| * | Implement spill and fill of I64Regs. | Jakob Stoklund Olesen | 2013-05-20 | 1 | -2/+9 |
| * | Mark i64 SETCC as expand so it is turned into a SELECT_CC. | Jakob Stoklund Olesen | 2013-05-20 | 1 | -0/+2 |
| * | Replace some bit operations with simpler ones. No functionality change. | Benjamin Kramer | 2013-05-19 | 3 | -12/+9 |
| * | Don't use %g0 to materialize 0 directly. | Jakob Stoklund Olesen | 2013-05-19 | 2 | -4/+2 |
| * | Select i64 values with %icc conditions. | Jakob Stoklund Olesen | 2013-05-19 | 1 | -0/+5 |
| * | Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072> | Bob Wilson | 2013-05-19 | 1 | -0/+3 |
| * | Add floating point selects on %xcc predicates. | Jakob Stoklund Olesen | 2013-05-19 | 1 | -0/+10 |
| * | Implement SPselectfcc for i64 operands. | Jakob Stoklund Olesen | 2013-05-19 | 2 | -27/+31 |
| * | [Sparc] Rearrange integer registers' allocation order so that register alloca... | Venkatraman Govindaraju | 2013-05-19 | 2 | -10/+23 |
| * | Handle i64 FrameIndex nodes in SPARC v9 mode. | Jakob Stoklund Olesen | 2013-05-19 | 1 | -1/+1 |
| * | AArch64: make RuntimeDyld relocations idempotent | Tim Northover | 2013-05-19 | 1 | -2/+22 |
| * | Invalidate instruction cache when setting memory to be executable. | Tim Northover | 2013-05-19 | 1 | -0/+3 |
| * | isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also. | David Majnemer | 2013-05-18 | 1 | -0/+11 |
| * | LoopVectorize: Handle single edge PHIs | Arnold Schwaighofer | 2013-05-18 | 1 | -4/+4 |
| * | Check InlineAsm clobbers in PPCCTRLoops | Hal Finkel | 2013-05-18 | 1 | -0/+15 |
| * | AArch64: add CMake dependency to fix very parallel builds | Tim Northover | 2013-05-18 | 1 | -0/+2 |
| * | X86: Bad peephole interaction between adc, MOV32r0 | David Majnemer | 2013-05-18 | 1 | -3/+18 |
| * | Remove duplicated comment | Matt Arsenault | 2013-05-18 | 1 | -5/+0 |
