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* Add POWER6 and POWER7 CPU types to the PPC backend.Hal Finkel2012-06-113-0/+14
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-1/+4
* Re-enable the CMN instruction.Bill Wendling2012-06-115-69/+144
* InstCombine: factor code better.Benjamin Kramer2012-06-111-14/+7
* InstCombine: Turn (zext A) == (B & (1<<X)-1) into A == (trunc B), narrowing t...Benjamin Kramer2012-06-101-1/+23
* Enable ILP scheduling for all nodes by default on PPC.Hal Finkel2012-06-101-4/+6
* Add AutoUpgrade support for the SSE4 ptest intrinsics.Nadav Rotem2012-06-101-6/+59
* Use critical anti-dep. breaking on all PPC targets, but also add other regist...Hal Finkel2012-06-101-4/+11
* Add intrinsics for immediate form of XOP vprot instructions. Use i128mem inst...Craig Topper2012-06-101-27/+37
* Improve ext/trunc patterns on PPC64.Hal Finkel2012-06-091-11/+4
* Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type...Craig Topper2012-06-094-60/+13
* Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as...Craig Topper2012-06-092-175/+67
* Disabling a spurious deprecation warning about using PathV1 from within the P...Aaron Ballman2012-06-091-0/+10
* Fixing a typo in the comments.Aaron Ballman2012-06-091-1/+1
* Allocate the contents of DwarfDebug's StringMaps in a single big BumpPtrAlloc...Benjamin Kramer2012-06-092-5/+6
* Silence a gcc-4.6 warning: GCC fails to understand that secondReg and cmpOp2 areDuncan Sands2012-06-091-1/+1
* Enable tail merging on PPC.Hal Finkel2012-06-091-7/+1
* Register pressure: added getPressureAfterInstr.Andrew Trick2012-06-091-33/+80
* Sketch a LiveRegMatrix analysis pass.Jakob Stoklund Olesen2012-06-093-0/+296
* Test commitJack Carter2012-06-091-0/+1
* Also compute MBB live-in lists in the new rewriter pass.Jakob Stoklund Olesen2012-06-096-89/+32
* Convert comments to proper Doxygen comments.Dmitri Gribenko2012-06-093-11/+11
* Reintroduce VirtRegRewriter.Jakob Stoklund Olesen2012-06-087-78/+121
* canonicalize:Nuno Lopes2012-06-081-4/+5
* Start implementing pre-ra if-converter: using speculation and selects to elim...Evan Cheng2012-06-081-6/+15
* TargetInstrInfo hooks implemented in codegen should be declared pure virtual.Andrew Trick2012-06-081-13/+13
* Reapply commit 158073 with a fix (the testcase was already committed). TheDuncan Sands2012-06-081-123/+120
* Remove the TODO statement in the PPC README re: CTR loopsHal Finkel2012-06-081-1/+0
* Enable PPC CTR loop formation by default.Hal Finkel2012-06-082-11/+9
* Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.Hal Finkel2012-06-081-2/+10
* Enable optimization for integer ABS on X86 if Subtarget has CMOV.Manman Ren2012-06-081-3/+5
* Fix a crash in APInt::lshr when shiftAmt > BitWidth.Chad Rosier2012-06-081-1/+1
* Fix Target->Codegen dependence.Andrew Trick2012-06-082-195/+205
* BoundsChecking: add support for ConstantPointerNull. fixes a bunch of instrum...Nuno Lopes2012-06-081-6/+7
* Disable the PPC CTR-Loops pass by default.Hal Finkel2012-06-082-4/+17
* Fix a bug in the new PPC CTR-Loops pass.Hal Finkel2012-06-081-0/+1
* Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ...Hal Finkel2012-06-089-18/+812
* Revert commit 158073 while waiting for a fix. The issue is that reassociateDuncan Sands2012-06-081-111/+123
* X86: optimize generated code for integer ABSManman Ren2012-06-071-2/+44
* Do not optimize the used bits of the x86 vselect condition operand, when the ...Nadav Rotem2012-06-071-4/+6
* Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector elem...Nadav Rotem2012-06-071-0/+6
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-072-24/+67
* ARM getOperandLatency rewrite.Andrew Trick2012-06-071-85/+112
* ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick2012-06-071-1/+4
* Fix ARM getInstrLatency logic to work with the current API.Andrew Trick2012-06-071-13/+19
* PR13046: we can't replace usage of SUB with CMP in the lowering phase.Manman Ren2012-06-071-1/+2
* Use a base register instead of an index register with the local dynamic model.Rafael Espindola2012-06-071-0/+8
* Move terminator machine verification to check MachineBasicBlock::instr_iterat...Pete Cooper2012-06-071-11/+11
* X86: replace SUB with CMP if possibleManman Ren2012-06-071-1/+14
* Revert r157755.Manman Ren2012-06-063-42/+0
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