| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Print a space after the colon. | Mikhail Glushenkov | 2010-05-20 | 1 | -2/+2 |
| * | Make Solve check its own post-condition, to reduce clutter in the | Dan Gohman | 2010-05-20 | 1 | -1/+2 |
| * | Add comments. | Dan Gohman | 2010-05-20 | 1 | -0/+16 |
| * | MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with ... | Daniel Dunbar | 2010-05-20 | 1 | -0/+7 |
| * | Rename variable. add comment. | Devang Patel | 2010-05-20 | 1 | -2/+5 |
| * | More code cleanups. Use iterators instead of indices when indices | Dan Gohman | 2010-05-20 | 1 | -22/+24 |
| * | X86: Model i64i32imm properly, as a subclass of all immediates. | Daniel Dunbar | 2010-05-20 | 3 | -2/+29 |
| * | X86: Fix immediate type of FOO64i32 operations. | Daniel Dunbar | 2010-05-20 | 1 | -10/+10 |
| * | Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set | Dan Gohman | 2010-05-20 | 1 | -8/+7 |
| * | Add some comments. | Dan Gohman | 2010-05-20 | 1 | -0/+6 |
| * | Simplify this code. Don't do a DomTreeNode lookup for each visited block. | Dan Gohman | 2010-05-20 | 1 | -14/+5 |
| * | Refactor. | Devang Patel | 2010-05-20 | 2 | -37/+76 |
| * | Grammar fix. This is a test commit. | Matt Fleming | 2010-05-20 | 1 | -1/+1 |
| * | Minor code cleanups. | Dan Gohman | 2010-05-20 | 1 | -20/+11 |
| * | When canonicalizing icmp operand order to put the loop invariant | Dan Gohman | 2010-05-20 | 1 | -0/+1 |
| * | llvmc: Make segfault detection work on Win32. | Mikhail Glushenkov | 2010-05-20 | 1 | -21/+28 |
| * | Set Changed to true when canonicalizing ICmp operand order; even though | Dan Gohman | 2010-05-20 | 1 | -0/+1 |
| * | Handle Neon v2f64 and v2i64 vector shuffles as register copies. | Bob Wilson | 2010-05-20 | 1 | -0/+18 |
| * | Remove dbg_value workaround and associated command line option | Jim Grosbach | 2010-05-20 | 1 | -20/+0 |
| * | Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't | Dan Gohman | 2010-05-20 | 1 | -3/+0 |
| * | The PPC MFCR instruction implicitly uses all 8 of the CR | Dale Johannesen | 2010-05-20 | 5 | -21/+24 |
| * | Strip llvm.dbg.lv also. | Devang Patel | 2010-05-20 | 1 | -0/+6 |
| * | Rename a variable to avoid shadowing. | Dan Gohman | 2010-05-20 | 1 | -2/+3 |
| * | Split DbgVariable. Eventually, variable info will be communicated through fra... | Devang Patel | 2010-05-20 | 2 | -94/+111 |
| * | Minor code simplification. | Dan Gohman | 2010-05-20 | 1 | -4/+4 |
| * | Fix assembly parsing and encoding of the pushf and popf family of | Dan Gohman | 2010-05-20 | 4 | -10/+31 |
| * | Set neverHasSideEffects on 64-bit pushf and popf, for consistency with | Dan Gohman | 2010-05-20 | 1 | -2/+2 |
| * | Move the code for deleting BaseRegs and LSRUses into helper functions, | Dan Gohman | 2010-05-20 | 1 | -5/+22 |
| * | Reduce string trashing. | Benjamin Kramer | 2010-05-20 | 1 | -2/+2 |
| * | Add a hybrid bottom up scheduler that reduce register usage while avoiding | Evan Cheng | 2010-05-20 | 4 | -28/+141 |
| * | Fix typo in comment. | Nick Lewycky | 2010-05-20 | 1 | -2/+2 |
| * | Define the x86 pause instruction. | Dan Gohman | 2010-05-20 | 1 | -0/+4 |
| * | Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it | Dan Gohman | 2010-05-20 | 1 | -1/+2 |
| * | Partial code for emitting thread local bss data. | Eric Christopher | 2010-05-20 | 3 | -0/+9 |
| * | Teach LSR how to cope better with unrolled loops on targets where | Dan Gohman | 2010-05-19 | 1 | -3/+191 |
| * | Optimize away insertelement of an undef value. This shows up in | Bob Wilson | 2010-05-19 | 1 | -0/+4 |
| * | fix rdar://7986634 - match instruction opcodes case insensitively. | Chris Lattner | 2010-05-19 | 1 | -1/+6 |
| * | Enable preserving debug information through post-RA scheduling | Jim Grosbach | 2010-05-19 | 1 | -1/+1 |
| * | Fix the post-RA instruction scheduler to handle instructions referenced by | Jim Grosbach | 2010-05-19 | 1 | -3/+3 |
| * | Code clean up. | Evan Cheng | 2010-05-19 | 1 | -7/+7 |
| * | Revert r104165. | Devang Patel | 2010-05-19 | 2 | -5/+13 |
| * | Add support for partial redefs to the fast register allocator. | Jakob Stoklund Olesen | 2010-05-19 | 1 | -20/+18 |
| * | There is no need to maintain InsnsBeginScopeSet separately. | Devang Patel | 2010-05-19 | 2 | -13/+5 |
| * | Add MachineInstr::readsVirtualRegister() in preparation for proper handling of | Jakob Stoklund Olesen | 2010-05-19 | 1 | -1/+24 |
| * | Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMa... | Evan Cheng | 2010-05-19 | 8 | -10/+10 |
| * | TwoAddressInstructionPass doesn't really know how to merge live intervals when | Jakob Stoklund Olesen | 2010-05-19 | 1 | -1/+6 |
| * | llvmc: report an error if a child process segfaults. | Mikhail Glushenkov | 2010-05-19 | 1 | -1/+14 |
| * | When expanding a vector_shuffle, the element type may not be legal and may | Bob Wilson | 2010-05-19 | 1 | -0/+2 |
| * | MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode(). | Daniel Dunbar | 2010-05-19 | 1 | -0/+1 |
| * | MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same | Daniel Dunbar | 2010-05-19 | 2 | -0/+17 |
