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* The vbroadcast family of instructions has 'fallback patterns' in case where theNadav Rotem2012-07-181-6/+8
| | | | | | | | | | | | | | load source operand is used by multiple nodes. The v2i64 broadcast was emulated by shuffling the two lower i32 elements to the upper two. We had a bug in the immediate used for the broadcast. Replacing 0 to 0x44. 0x44 means [01|00|01|00] which corresponds to the correct lane. Patch by Michael Kuperstein. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160430 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific inline asm operand modifier 'M':Jack Carter2012-07-181-3/+8
| | | | | | | | | | | | | | | | | | | | | | | Print the high order register of a double word register operand. In 32 bit mode, a 64 bit double word integer will be represented by 2 32 bit registers. This modifier causes the high order register to be used in the asm expression. It is useful if you are using doubles in assembler and continue to control register to variable relationships. This patch also fixes a related bug in a previous patch: case 'D': // Second part of a double word register operand case 'L': // Low order register of a double word register operand case 'M': // High order register of a double word register operand I got 'D' and 'M' confused. The second part of a double word operand will only match 'M' for one of the endianesses. I had 'L' and 'D' be the opposite twins when 'L' and 'M' are. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160429 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tab characters.Craig Topper2012-07-181-13/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160425 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in error message and remove some tab characters.Craig Topper2012-07-181-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160423 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars: drive by heuristics fix.Andrew Trick2012-07-181-1/+1
| | | | | | Minor oversight noticed by inspection. Sorry no unit test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160422 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars: Linear function test replace should avoid reusing undef.Andrew Trick2012-07-181-5/+67
| | | | | | | | | | | | | | | | | | | | | | | Fixes PR13371: indvars pass incorrectly substitutes 'undef' values. I do not like this fix. It's needed until/unless the meaning of undef changes. It attempts to be complete according to the IR spec, but I don't have much confidence in the implementation given the difficulty testing undefined behavior. Worse, this invalidates some of my hard-fought work on indvars and LSR to optimize pointer induction variables. It results benchmark regressions, which I'll track internally. On x86_64 no LTO I see: -3% huffbench -3% 400.perlbench -8% fhourstones My only suggestion for recovering is to change the meaning of undef. If we could trust an arbitrary instruction to produce a some real value that can be manipulated (e.g. incremented) according to non-undef rules, then this case could be easily handled with SCEV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160421 91177308-0d34-0410-b5e6-96231b3b80d8
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-183-15/+66
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed few warnings.Galina Kistanova2012-07-181-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160419 91177308-0d34-0410-b5e6-96231b3b80d8
* ignore 'invoke @llvm.donothing', but still keep the edge to the continuation BBNuno Lopes2012-07-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160411 91177308-0d34-0410-b5e6-96231b3b80d8
* More replacing of target-dependent intrinsics with target-indepdent Joel Jones2012-07-182-3/+13
| | | | | | | | | | | | | | | | | | | | | | intrinsics. The second instruction(s) to be handled are the vector versions of count set bits (ctpop). The changes here are to clang so that it generates a target independent vector ctpop when it sees an ARM dependent vector bits set count. The changes in llvm are to match the target independent vector ctpop and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector pop counts with target-independent ctpops. There are also changes to an existing test case in llvm for ARM vector count instructions and to a test for the bitcode upgrade. <rdar://problem/11892519> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160410 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.Akira Hatanaka2012-07-172-93/+117
| | | | | | | Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160403 91177308-0d34-0410-b5e6-96231b3b80d8
* Back out r160101 and instead implement a dag combine to recover from ↵Evan Cheng2012-07-173-7/+29
| | | | | | instcombine transformation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160387 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some trace output to TwoAddressInstructionPass.Jakob Stoklund Olesen2012-07-171-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160380 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused variable.Benjamin Kramer2012-07-171-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160372 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify getSetSize() per Duncan's commentsNuno Lopes2012-07-171-6/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160368 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve behavior of DebugInfoEntryMinimal::getSubprogramName() introduced in ↵Alexey Samsonov2012-07-173-28/+35
| | | | | | | | | | | | r159512. To fetch a subprogram name we should not only inspect the DIE for this subprogram, but optionally inspect its specification, or its abstract origin (even if there is no inlining), or even specification of an abstract origin. Reviewed by Benjamin Kramer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160365 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] more code to merge crash callbacks. Doesn't fully work yet, but ↵Kostya Serebryany2012-07-171-12/+58
| | | | | | allows to hold performance experiments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160361 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a crash in the legalization of large vectors.Nadav Rotem2012-07-171-6/+3
| | | | | | | | | When truncating a result of a vector that is split we need to use the result of the split vector, and not re-split the dead node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160357 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement r160312 as target indepedenet dag combine.Evan Cheng2012-07-172-44/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160354 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure constant bitwidth is <= 64 bit before calling getSExtValue().Evan Cheng2012-07-171-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160350 91177308-0d34-0410-b5e6-96231b3b80d8
* This is another case where instcombine demanded bits optimization createdEvan Cheng2012-07-173-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160346 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r160340. LSR: Limit CollectSubexprs.Andrew Trick2012-07-171-28/+52
| | | | | | Speculatively fix crashes by code inspection. Can't reproduce them yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160344 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "LSR: try not to blow up solving combinatorial problems brute force."Andrew Trick2012-07-171-51/+28
| | | | | | Some units tests crashed on a different platform. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160341 91177308-0d34-0410-b5e6-96231b3b80d8
* LSR: try not to blow up solving combinatorial problems brute force.Andrew Trick2012-07-171-28/+51
| | | | | | | | | | This places limits on CollectSubexprs to constrains the number of reassociation possibilities. It limits the recursion depth and skips over chains of nested recurrences outside the current loop. Fixes PR13361. Although underlying SCEV behavior is still potentially bad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160340 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR13339 (remove the predecessor from the unwind BB when removing an invoke)Nuno Lopes2012-07-161-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160325 91177308-0d34-0410-b5e6-96231b3b80d8
* teach ConstantRange that zero times X is always zeroNuno Lopes2012-07-161-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160317 91177308-0d34-0410-b5e6-96231b3b80d8
* For something likeEvan Cheng2012-07-161-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | uint32_t hi(uint64_t res) { uint_32t hi = res >> 32; return !hi; } llvm IR looks like this: define i32 @hi(i64 %res) nounwind uwtable ssp { entry: %lnot = icmp ult i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext } The optimizer has optimize away the right shift and truncate but the resulting constant is too large to fit in the 32-bit immediate field. The resulting x86 code is worse as a result: movabsq $4294967296, %rax ## imm = 0x100000000 cmpq %rax, %rdi sbbl %eax, %eax andl $1, %eax This patch teaches the x86 lowering code to handle ult against a large immediate with trailing zeros. It will issue a right shift and a truncate followed by a comparison against a shifted immediate. shrq $32, %rdi testl %edi, %edi sete %al movzbl %al, %eax It also handles a ugt comparison against a large immediate with trailing bits set. i.e. X > 0x0ffffffff -> (X >> 32) >= 1 rdar://11866926 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160312 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanup and docs.Nadav Rotem2012-07-161-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160311 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ComputeDemandedBits return a deterministic result when computing an ↵Nadav Rotem2012-07-161-0/+1
| | | | | | | | | | | | | AssertZext value. In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits reported that some of the bits were both known to be one and known to be zero. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160305 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-16114-28329/+0
| | | | | | This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Build script changes for R600/SI Codegen v6"Tom Stellard2012-07-161-1/+1
| | | | | | This reverts commit e3013202259ed1e006c21817c63cf25d75982721. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160301 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, ↵Tom Stellard2012-07-161-2/+2
| | | | | | | | <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>" This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160299 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵Tom Stellard2012-07-162-3/+1
| | | | | | | | AMDGPUCommonTableGen." This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160298 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as ↵Tom Stellard2012-07-161-8/+8
| | | | | | | | conditional operator..." This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160297 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in ↵Tom Stellard2012-07-161-1/+1
| | | | | | | | nonreturn function, instead of assert(0)." This reverts commit 4ba4acc1bc2561b944a571edbb6a2dc78e357dfe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160296 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Target/AMDGPU: Fix includes, or msvc build failed."Tom Stellard2012-07-162-2/+2
| | | | | | This reverts commit fef4aa1b16fcf7a472559abbbcf4c1adc9eb5ca6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160295 91177308-0d34-0410-b5e6-96231b3b80d8
* make ConstantRange::getSetSize() properly compute the size of wrapped and ↵Nuno Lopes2012-07-161-8/+10
| | | | | | | | full sets. Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160294 91177308-0d34-0410-b5e6-96231b3b80d8
* With r160248 in place this code is no longer needed.Chad Rosier2012-07-162-17/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160293 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] a bit more refactoring, addressed some of the style comments from ↵Kostya Serebryany2012-07-161-17/+39
| | | | | | chandlerc, partially implemented crash callback merging (under flag) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160290 91177308-0d34-0410-b5e6-96231b3b80d8
* MSVC's implementation of isalnum will assert on characters > 255, so we need ↵Aaron Ballman2012-07-161-1/+5
| | | | | | to use an unsigned char to ensure the integer promotion happens properly. This fixes an assert in debug builds with CodeGen\X86\utf8.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160286 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] refactor instrumentation to allow merging the crash callbacks (not ↵Kostya Serebryany2012-07-161-48/+93
| | | | | | fully implemented yet, no functionality change except the BB order) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160284 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/AMDGPU: Fix includes, or msvc build failed.NAKAMURA Takumi2012-07-162-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160280 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn ↵NAKAMURA Takumi2012-07-161-1/+1
| | | | | | function, instead of assert(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160279 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional ↵NAKAMURA Takumi2012-07-161-8/+8
| | | | | | operator... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160278 91177308-0d34-0410-b5e6-96231b3b80d8
* Doubleword Shift Left Logical Plus 32Jack Carter2012-07-164-1/+57
| | | | | | | | | | | | | | | | | | | | | | Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵NAKAMURA Takumi2012-07-162-1/+3
| | | | | | AMDGPUCommonTableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160276 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> ↵NAKAMURA Takumi2012-07-161-2/+2
| | | | | | and <llvm/TypeBuilder.h> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160275 91177308-0d34-0410-b5e6-96231b3b80d8
* Build script changes for R600/SI Codegen v6Tom Stellard2012-07-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160272 91177308-0d34-0410-b5e6-96231b3b80d8
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-16114-0/+28329
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] initialize asan error callbacks in runOnModule instead of doing that ↵Kostya Serebryany2012-07-161-8/+20
| | | | | | on-demand git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160269 91177308-0d34-0410-b5e6-96231b3b80d8
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