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* Reapply commit 158073 with a fix (the testcase was already committed). TheDuncan Sands2012-06-081-123/+120
* Remove the TODO statement in the PPC README re: CTR loopsHal Finkel2012-06-081-1/+0
* Enable PPC CTR loop formation by default.Hal Finkel2012-06-082-11/+9
* Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.Hal Finkel2012-06-081-2/+10
* Enable optimization for integer ABS on X86 if Subtarget has CMOV.Manman Ren2012-06-081-3/+5
* Fix a crash in APInt::lshr when shiftAmt > BitWidth.Chad Rosier2012-06-081-1/+1
* Fix Target->Codegen dependence.Andrew Trick2012-06-082-195/+205
* BoundsChecking: add support for ConstantPointerNull. fixes a bunch of instrum...Nuno Lopes2012-06-081-6/+7
* Disable the PPC CTR-Loops pass by default.Hal Finkel2012-06-082-4/+17
* Fix a bug in the new PPC CTR-Loops pass.Hal Finkel2012-06-081-0/+1
* Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ...Hal Finkel2012-06-089-18/+812
* Revert commit 158073 while waiting for a fix. The issue is that reassociateDuncan Sands2012-06-081-111/+123
* X86: optimize generated code for integer ABSManman Ren2012-06-071-2/+44
* Do not optimize the used bits of the x86 vselect condition operand, when the ...Nadav Rotem2012-06-071-4/+6
* Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector elem...Nadav Rotem2012-06-071-0/+6
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-072-24/+67
* ARM getOperandLatency rewrite.Andrew Trick2012-06-071-85/+112
* ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick2012-06-071-1/+4
* Fix ARM getInstrLatency logic to work with the current API.Andrew Trick2012-06-071-13/+19
* PR13046: we can't replace usage of SUB with CMP in the lowering phase.Manman Ren2012-06-071-1/+2
* Use a base register instead of an index register with the local dynamic model.Rafael Espindola2012-06-071-0/+8
* Move terminator machine verification to check MachineBasicBlock::instr_iterat...Pete Cooper2012-06-071-11/+11
* X86: replace SUB with CMP if possibleManman Ren2012-06-071-1/+14
* Revert r157755.Manman Ren2012-06-063-42/+0
* Properly verify liveness with bundled machine instructions.Jakob Stoklund Olesen2012-06-061-13/+34
* Add accessors for all private members of DisasmContext.Benjamin Kramer2012-06-061-0/+8
* Move RegisterClassInfo.h.Andrew Trick2012-06-0611-143/+11
* Move RegisterPressure.h.Andrew Trick2012-06-064-258/+3
* Round 2 of dead private variable removal.Benjamin Kramer2012-06-0614-43/+14
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-0617-29/+13
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-06-063-14/+93
* Fix combine of uno && ord -> false so that the ordering of the fcmps doesn'tChad Rosier2012-06-061-1/+3
* Remove dead debug option -disable-rematerialization.Jakob Stoklund Olesen2012-06-061-4/+0
* Grab-bag of reassociate tweaks. Unify handling of dead instructions andDuncan Sands2012-06-061-123/+111
* Stop leaking RegScavengers from TailDuplication.Benjamin Kramer2012-06-061-3/+4
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-2/+2
* Mark several instructions SSE2 instead of SSE3 as they should be.Craig Topper2012-06-062-9/+11
* Move LiveUnionArray into LiveIntervalUnion.hJakob Stoklund Olesen2012-06-054-47/+54
* Don't print register names in LiveIntervalUnion::print().Jakob Stoklund Olesen2012-06-053-5/+2
* Suppress -Wunused-variable in -Asserts buildMatt Beaumont-Gay2012-06-051-0/+1
* Simplify LiveInterval::print().Jakob Stoklund Olesen2012-06-054-48/+19
* Add experimental support for register unit liveness.Jakob Stoklund Olesen2012-06-051-0/+130
* Implement LiveRangeCalc::extendToUses() and createDeadDefs().Jakob Stoklund Olesen2012-06-053-2/+103
* MachineInstr::eraseFromParent fix for removing bundled instrs.Andrew Trick2012-06-051-1/+2
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-057-118/+226
* Add a new intrinsic: llvm.fmuladd. This intrinsic represents a multiply-addLang Hames2012-06-051-0/+21
* Fix header file include order in NVPTX backend NV_CONTRIBYuan Lin2012-06-051-2/+2
* LoopUnroll: always check for NULL LoopPassManagerAndrew Trick2012-06-051-3/+5
* PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky2012-06-051-3/+3
* X86 itinerary properties.Andrew Trick2012-06-052-2/+29
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