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* X86: optimize generated code for integer ABSManman Ren2012-06-071-2/+44
| | | | | | | | | | | | | | | | | | | | | This patch will generate the following for integer ABS: movl %edi, %eax negl %eax cmovll %edi, %eax INSTEAD OF movl %edi, %ecx sarl $31, %ecx leal (%rdi,%rcx), %eax xorl %ecx, %eax There exists a target-independent DAG combine for integer ABS, which converts integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov. This is implemented in PerformXorCombine. rdar://10695237 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158175 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not optimize the used bits of the x86 vselect condition operand, when the ↵Nadav Rotem2012-06-071-4/+6
| | | | | | | | | | condition operand is a vector of 1-bit predicates. This may happen on MIC devices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector ↵Nadav Rotem2012-06-071-0/+6
| | | | | | elements, which may disagree with the select condition type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158166 91177308-0d34-0410-b5e6-96231b3b80d8
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-072-24/+67
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM getOperandLatency rewrite.Andrew Trick2012-06-071-85/+112
| | | | | | Match expectations of the new latency API. Cleanup and make the logic consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick2012-06-071-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM getInstrLatency logic to work with the current API.Andrew Trick2012-06-071-13/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
* PR13046: we can't replace usage of SUB with CMP in the lowering phase.Manman Ren2012-06-071-1/+2
| | | | | | | It will cause assertion failure later on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158160 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a base register instead of an index register with the local dynamic model.Rafael Espindola2012-06-071-0/+8
| | | | | | Fixes pr13048. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158 91177308-0d34-0410-b5e6-96231b3b80d8
* Move terminator machine verification to check ↵Pete Cooper2012-06-071-11/+11
| | | | | | MachineBasicBlock::instr_iterator instead of MBB::iterator git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158154 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: replace SUB with CMP if possibleManman Ren2012-06-071-1/+14
| | | | | | | | | | | | | | | | | | | This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r157755.Manman Ren2012-06-063-42/+0
| | | | | | | | | The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly verify liveness with bundled machine instructions.Jakob Stoklund Olesen2012-06-061-13/+34
| | | | | | | | Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158116 91177308-0d34-0410-b5e6-96231b3b80d8
* Add accessors for all private members of DisasmContext.Benjamin Kramer2012-06-061-0/+8
| | | | | | LLVM should be -Wunused-private-field clean now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158103 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterClassInfo.h.Andrew Trick2012-06-0611-143/+11
| | | | | | | Allow targets to access this API. It's required for RegisterPressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterPressure.h.Andrew Trick2012-06-064-258/+3
| | | | | | | Make it a general utility for use by Targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097 91177308-0d34-0410-b5e6-96231b3b80d8
* Round 2 of dead private variable removal.Benjamin Kramer2012-06-0614-43/+14
| | | | | | | | LLVM is now -Wunused-private-field clean except for - lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields. - gtest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-0617-29/+13
| | | | | | | | There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-06-063-14/+93
| | | | | | | | X86. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158087 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix combine of uno && ord -> false so that the ordering of the fcmps doesn'tChad Rosier2012-06-061-1/+3
| | | | | | | | matter. rdar://11579835 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158084 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead debug option -disable-rematerialization.Jakob Stoklund Olesen2012-06-061-4/+0
| | | | | | | Remat has been stable for years, and it isn't done by LiveIntervalAnalysis any longer. (See LiveRangeEdit). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158079 91177308-0d34-0410-b5e6-96231b3b80d8
* Grab-bag of reassociate tweaks. Unify handling of dead instructions andDuncan Sands2012-06-061-123/+111
| | | | | | | | | | instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158073 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop leaking RegScavengers from TailDuplication.Benjamin Kramer2012-06-061-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158069 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark several instructions SSE2 instead of SSE3 as they should be.Craig Topper2012-06-062-9/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
* Move LiveUnionArray into LiveIntervalUnion.hJakob Stoklund Olesen2012-06-054-47/+54
| | | | | | It is useful outside RegAllocBase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158041 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't print register names in LiveIntervalUnion::print().Jakob Stoklund Olesen2012-06-053-5/+2
| | | | | | | | Soon we'll be making LiveIntervalUnions for register units as well. This was the only place using the RepReg member, so just remove it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158038 91177308-0d34-0410-b5e6-96231b3b80d8
* Suppress -Wunused-variable in -Asserts buildMatt Beaumont-Gay2012-06-051-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158037 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify LiveInterval::print().Jakob Stoklund Olesen2012-06-054-48/+19
| | | | | | | | | | Don't print out the register number and spill weight, making the TRI argument unnecessary. This allows callers to interpret the reg field. It can currently be a virtual register, a physical register, a spill slot, or a register unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158031 91177308-0d34-0410-b5e6-96231b3b80d8
* Add experimental support for register unit liveness.Jakob Stoklund Olesen2012-06-051-0/+130
| | | | | | | | | | | | | | | | Instead of computing a live interval per physreg, LiveIntervals can compute live intervals per register unit. This makes impossible the confusing situation where aliasing registers could have overlapping live intervals. It should also make fixed interferernce checking cheaper since registers have fewer register units than aliases. Live intervals for regunits are computed on demand, using MRI use-def chains and the new LiveRangeCalc class. Only regunits live in to ABI blocks are precomputed during LiveIntervals::runOnMachineFunction(). The regunit liveness computations don't depend on LiveVariables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158029 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement LiveRangeCalc::extendToUses() and createDeadDefs().Jakob Stoklund Olesen2012-06-053-2/+103
| | | | | | | These LiveRangeCalc methods are to be used when computing a live range from scratch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158027 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineInstr::eraseFromParent fix for removing bundled instrs.Andrew Trick2012-06-051-1/+2
| | | | | | Patch by Ivan Llopard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158025 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-057-118/+226
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new intrinsic: llvm.fmuladd. This intrinsic represents a multiply-addLang Hames2012-06-051-0/+21
| | | | | | | | | | | | | | expression (a * b + c) that can be implemented as a fused multiply-add (fma) if the target determines that this will be more efficient. This intrinsic will be used to implement FP_CONTRACT support and an aggressive FMA formation mode. If your target has a fast FMA instruction you should override the isFMAFasterThanMulAndAdd method in TargetLowering to return true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158014 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix header file include order in NVPTX backend NV_CONTRIBYuan Lin2012-06-051-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158013 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopUnroll: always check for NULL LoopPassManagerAndrew Trick2012-06-051-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158007 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky2012-06-051-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158004 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 itinerary properties.Andrew Trick2012-06-052-2/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM itinerary properties.Andrew Trick2012-06-053-22/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Added MultiIssueItineraries.Andrew Trick2012-06-058-22/+22
| | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
* sdsched: Use the right heuristics when -mcpu is not provided and we have no ↵Andrew Trick2012-06-051-13/+12
| | | | | | | | itinerary. Use ILP heuristics for long latency instrs if no scoreboard exists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157978 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Allow disabling scoreboard hazard checking for subtargets with aAndrew Trick2012-06-051-6/+12
| | | | | | | | valid itinerary but no pipeline stages. An itinerary can contain useful scheduling information without specifying pipeline stages for each instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157977 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-06-052-5/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: comments from code review.Andrew Trick2012-06-051-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157975 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the last remat-related code from LiveIntervalAnalysis.Jakob Stoklund Olesen2012-06-051-95/+0
| | | | | | Rematerialization is handled by LiveRangeEdit now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157974 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop using LiveIntervals::isReMaterializable().Jakob Stoklund Olesen2012-06-051-9/+24
| | | | | | | | | | It is an old function that does a lot more than required by CalcSpillWeights, which was the only remaining caller. The isRematerializable() function never actually sets the isLoad argument, so don't try to compute that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157973 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert commit r157966Joel Jones2012-06-051-24/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157972 91177308-0d34-0410-b5e6-96231b3b80d8
* This change handles a another case for generating the bic instruction Joel Jones2012-06-041-0/+24
| | | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157966 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete dead code.Jakob Stoklund Olesen2012-06-041-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157963 91177308-0d34-0410-b5e6-96231b3b80d8
* When gvn decides to replace an instruction with another, we have to patch theRafael Espindola2012-06-041-2/+200
| | | | | | | | | | | | replacement to make it at least as generic as the instruction being replaced. This includes: * dropping nsw/nuw flags * getting the least restrictive tbaa and fpmath metadata * merging ranges Fixes PR12979. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157958 91177308-0d34-0410-b5e6-96231b3b80d8
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