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* Support for Hexagon feature, New Value Jump.Sirish Pande2012-05-127-2/+682
* Remove MipsEmitGPRestore.cpp.Akira Hatanaka2012-05-123-99/+0
* Delete all functions that are no longer needed in MipsFunctionInfo, includingAkira Hatanaka2012-05-122-15/+1
* Stop reserving register $gp. Do not call isGPFI to check whether a frame objectAkira Hatanaka2012-05-121-8/+1
* Do not add the pass which restores $gp after every function call.Akira Hatanaka2012-05-121-9/+0
* Make the following changes in MipsISelLowering.cpp:Akira Hatanaka2012-05-121-8/+8
* Make the following changes in MipsFrameLowering.cpp:Akira Hatanaka2012-05-121-32/+3
* Make the following changes in MipsAsmPrinter.cpp:Akira Hatanaka2012-05-123-31/+11
* Hoist simpler checks above llvm::PointerMayBeCaptured. No functional change i...Chad Rosier2012-05-121-4/+6
* Don't look for empty live ranges in the unions.Jakob Stoklund Olesen2012-05-121-1/+4
* Insert instructions to the entry basic block which initializes the globalAkira Hatanaka2012-05-121-35/+52
* Do not replace operands of pseudo instructions with register $zero.Akira Hatanaka2012-05-111-1/+2
* Revert 156658.Chad Rosier2012-05-111-2/+1
* [fast-isel] Fast-isel doesn't use the expect intrinsic.Chad Rosier2012-05-111-1/+2
* [Support/StringRef] Add find_last_not_of and {r,l,}trim.Michael J. Spencer2012-05-111-0/+26
* [fast-isel] Add support for selecting @llvm.trap().Chad Rosier2012-05-111-0/+4
* Updated instruction table due to addded intrinsics.Brendon Cahoon2012-05-111-1880/+1943
* Remove warnings from HexagonVLIWPacketizer.Sirish Pande2012-05-111-3/+3
* Hexagon constant extender support.Brendon Cahoon2012-05-1115-339/+3626
* Typo.Chad Rosier2012-05-111-1/+1
* [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Min...Chad Rosier2012-05-111-12/+2
* Hexagon V5 intrinsics support.Sirish Pande2012-05-113-615/+1061
* [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier2012-05-111-4/+21
* objectsize: add a few more tests and fix a bugNuno Lopes2012-05-111-1/+1
* [fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier2012-05-111-2/+4
* The return type is an unsigned, not a bool.Chad Rosier2012-05-111-1/+1
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-114-130/+350
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-114-16/+35
* Added the missing bit definition for the 4th bit of the STR (post reg) instru...Silviu Baranga2012-05-112-0/+5
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate o...Silviu Baranga2012-05-112-3/+9
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-1112-35/+35
* Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman2012-05-111-1/+1
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-112-27/+128
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-113-0/+8
* Allow unique_file to take a mode for file permissions, but defaultEric Christopher2012-05-112-5/+8
* Fix intendation.Chad Rosier2012-05-101-1/+1
* objectsize: add support for GEPs with non-constant indexesNuno Lopes2012-05-103-34/+34
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-103-223/+426
* Add support for the 'X' inline asm operand modifier.Eric Christopher2012-05-101-4/+16
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
* misched: Introducing Top and Bottom register pressure trackers during schedul...Andrew Trick2012-05-103-39/+112
* Hexagon V5 Support - V5 td file.Sirish Pande2012-05-101-0/+626
* Hexagon V5 FP Support.Sirish Pande2012-05-1014-194/+519
* RegPressure: API for speculatively checking instruction pressure.Andrew Trick2012-05-102-1/+229
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