aboutsummaryrefslogtreecommitdiffstats
path: root/lib
Commit message (Expand)AuthorAgeFilesLines
...
* sys::process::get_id() now returns the process ID instead of a process handle...Aaron Ballman2013-06-081-1/+1
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc bac...Venkatraman Govindaraju2013-06-087-162/+61
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-081-0/+4
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-081-1/+7
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-082-0/+34
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-081-2/+2
* Fix a potential bug in r183584.Shuxin Yang2013-06-081-4/+8
* Don't artifically restrict input object size.Sean Silva2013-06-081-2/+0
* Fix unused variable warning from my previous patch.JF Bastien2013-06-081-0/+1
* [mips] Use a helper function which compares the size of the source andAkira Hatanaka2013-06-082-8/+21
* Reapply r183552. This time, use a standard type for the option to avoid templateQuentin Colombet2013-06-081-0/+13
* R600: Use a refined heuristic to choose when switching clauseVincent Lejeune2013-06-072-10/+47
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-6/+4
* Remember the anyext patterns.Jakob Stoklund Olesen2013-06-071-0/+2
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+3
* Fix an assertion in MemCpyOpt pass.Shuxin Yang2013-06-071-2/+4
* Disallow i64 div/rem in PPC32 counter loopsHal Finkel2013-06-071-0/+7
* Revert commits related to stack warning.Quentin Colombet2013-06-071-13/+0
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-073-6/+6
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-077-16/+33
* Remove unused c'tor.Bill Wendling2013-06-071-7/+2
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-21/+2
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-8/+10
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-0736-1458/+218
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-9/+10
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0721-63/+75
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-074-27/+30
* R600: Move Subtarget feature definitions into AMDGPU.tdTom Stellard2013-06-072-64/+66
* R600: Remove unnecessary includeTom Stellard2013-06-073-2/+4
* Add a backend option to warn on a given stack size limit.Quentin Colombet2013-06-071-0/+13
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-071-38/+103
* R600: Don't compare iterators of different maps.Benjamin Kramer2013-06-071-1/+1
* Teach AsmPrinter how to print odd constants.Quentin Colombet2013-06-071-2/+43
* DIBuilder: No functionality change.Manman Ren2013-06-071-23/+26
* Vincent says the element is at most once in the vector, so we don't need a fu...Benjamin Kramer2013-06-071-3/+7
* Use isxdigit.Rafael Espindola2013-06-071-9/+1
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-1/+1
* Support OpenBSD's native frame protection conventions.Rafael Espindola2013-06-071-11/+36
* R600: Fix a potential iterator invalidation issue.Benjamin Kramer2013-06-071-5/+3
* R600: Remove an extra break in R600OptimizeVectorRegisters.cppVincent Lejeune2013-06-071-3/+1
* Fold variable that's only used in assert into the assert.Benjamin Kramer2013-06-071-2/+1
* Correct wrong register in this example, pointed out by Baoshan Pang.Duncan Sands2013-06-071-1/+1
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-077-20/+27
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0711-40/+67
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-073-6/+5
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-10/+6
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-079-19/+25
* [objc-arc] Ensure that the cfg path count does not overflow when we multiply ...Michael Gottesman2013-06-071-10/+38
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0715-42/+48
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-076-28/+22