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* Partial code for emitting thread local bss data.Eric Christopher2010-05-203-0/+9
* Teach LSR how to cope better with unrolled loops on targets whereDan Gohman2010-05-191-3/+191
* Optimize away insertelement of an undef value. This shows up inBob Wilson2010-05-191-0/+4
* fix rdar://7986634 - match instruction opcodes case insensitively.Chris Lattner2010-05-191-1/+6
* Enable preserving debug information through post-RA schedulingJim Grosbach2010-05-191-1/+1
* Fix the post-RA instruction scheduler to handle instructions referenced byJim Grosbach2010-05-191-3/+3
* Code clean up.Evan Cheng2010-05-191-7/+7
* Revert r104165.Devang Patel2010-05-192-5/+13
* Add support for partial redefs to the fast register allocator.Jakob Stoklund Olesen2010-05-191-20/+18
* There is no need to maintain InsnsBeginScopeSet separately. Devang Patel2010-05-192-13/+5
* Add MachineInstr::readsVirtualRegister() in preparation for proper handling ofJakob Stoklund Olesen2010-05-191-1/+24
* Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMa...Evan Cheng2010-05-198-10/+10
* TwoAddressInstructionPass doesn't really know how to merge live intervals whenJakob Stoklund Olesen2010-05-191-1/+6
* llvmc: report an error if a child process segfaults.Mikhail Glushenkov2010-05-191-1/+14
* When expanding a vector_shuffle, the element type may not be legal and mayBob Wilson2010-05-191-0/+2
* MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().Daniel Dunbar2010-05-191-0/+1
* MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid sameDaniel Dunbar2010-05-192-0/+17
* MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r andDaniel Dunbar2010-05-191-3/+5
* t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoi...Evan Cheng2010-05-192-0/+2
* Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.Evan Cheng2010-05-191-12/+4
* MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.Daniel Dunbar2010-05-191-9/+50
* Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These ...Evan Cheng2010-05-195-35/+37
* Target instruction selection should copy memoperands.Evan Cheng2010-05-191-3/+11
* MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, toDaniel Dunbar2010-05-191-6/+8
* Mark a few more pattern-less instructions with neverHasSideEffects. This is e...Evan Cheng2010-05-193-0/+12
* Add a comment explaining why this code uses Append mode.Dan Gohman2010-05-191-0/+4
* Intrinsics which do a vector compare (results are all zero or all ones) are m...Evan Cheng2010-05-191-6/+75
* Factor out the code for picking integer arithmetic with immediateDan Gohman2010-05-191-15/+32
* Add a comment.Dan Gohman2010-05-181-0/+1
* Fix the predicate which checks for non-sensical formulae which haveDan Gohman2010-05-181-4/+5
* Factor out the code for recomputing an LSRUse's Regs set after someDan Gohman2010-05-181-17/+40
* Fix a crash when debugging the coalescer. DebugValue instructions are notBob Wilson2010-05-181-4/+13
* Factor out code for estimating search space complexity into a helperDan Gohman2010-05-181-22/+26
* Add some more debug output.Dan Gohman2010-05-181-0/+1
* Factor out the code for deleting a formula from an LSRUse intoDan Gohman2010-05-181-4/+9
* Make some debug output more informative.Dan Gohman2010-05-181-2/+3
* Print an error message in Formula::print if the HasBaseReg flagDan Gohman2010-05-181-0/+7
* Rename RegUseTracker's RegUses member to RegUsesMap to avoidDan Gohman2010-05-181-7/+7
* Remember to update VirtRegLastUse when spilling without killing before a call.Jakob Stoklund Olesen2010-05-181-0/+10
* Teach mode load folding and unfolding code about CMP32ri8 and friends.Dan Gohman2010-05-181-3/+9
* Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" isBill Wendling2010-05-181-1/+1
* When converting a test to a cmp to fold a load, use the cmp that has anDan Gohman2010-05-181-3/+3
* make mcinstlower remove all but the first operand to CALL64pcrel32.Chris Lattner2010-05-181-1/+11
* Sink dag combine's post index load / store code that swap base ptr and index ...Evan Cheng2010-05-182-5/+15
* Implement EmitTBSSSymbol for MachOStreamer.Eric Christopher2010-05-181-5/+7
* Make EmitTBSSSymbol take a section argument so that we can find it later.Eric Christopher2010-05-183-9/+15
* Properly handle multiple definitions of a virtual register in the sameJakob Stoklund Olesen2010-05-181-21/+41
* Continuously refine the register class of REG_SEQUENCE def with all the sourc...Evan Cheng2010-05-181-2/+3
* Fix PR7162: Use source register classes and sub-indices to determine the corr...Evan Cheng2010-05-181-4/+6
* Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and notKevin Enderby2010-05-181-1/+1
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