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* Add writeAsHex(raw_ostream &) method to BinaryRef.Sean Silva2013-06-051-7/+14
* R600: Replace predicate loop with predicate functionTom Stellard2013-06-051-11/+13
* Rename BinaryRef::isBinary to more descriptive DataIsHexString.Sean Silva2013-06-051-1/+1
* Add space to assert message.Bill Wendling2013-06-051-1/+1
* Add writeAsBinary(raw_ostream &) method to BinaryRef.Sean Silva2013-06-051-0/+29
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-054-0/+370
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-052-1/+32
* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-051-0/+4
* Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit.Jakub Staszak2013-06-051-70/+56
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-052-1/+5
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-051-37/+49
* ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer2013-06-054-7/+89
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-051-0/+2
* This is a simple patch that changes RRX and RRXS to accept all registers as o...Mihai Popa2013-06-051-1/+1
* PR15662: Optimized debug info produces out of order function parametersDavid Blaikie2013-06-051-3/+31
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-053-4/+40
* Don't print default values for NumberOfAuxSymbols and AuxiliaryData.Rafael Espindola2013-06-051-2/+3
* Handle (at least don't crash on) relocations with no symbols.Rafael Espindola2013-06-051-6/+11
* Move BinaryRef to a new include/llvm/Object/YAML.h file.Rafael Espindola2013-06-053-17/+35
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-054-370/+0
* Handle relocations that don't point to symbols.Rafael Espindola2013-06-058-41/+28
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-044-0/+370
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-045-47/+186
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-041-1/+2
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-048-1277/+207
* ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer2013-06-041-0/+16
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-041-0/+364
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-041-0/+120
* ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer2013-06-041-0/+209
* ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer2013-06-041-0/+155
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-041-4/+45
* ARM sched model: Add branch thumb instructionsArnold Schwaighofer2013-06-041-18/+21
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-041-11/+15
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-041-27/+35
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-041-3/+6
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-041-2/+4
* ARM sched model: Add more ALU and CMP thumb instructionsArnold Schwaighofer2013-06-041-46/+61
* ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer2013-06-041-52/+86
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-041-37/+49
* ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer2013-06-044-7/+89
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-041-0/+2
* Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju2013-06-0419-154/+157
* IndVarSimplify: check if loop invariant expansion can trapDavid Majnemer2013-06-041-1/+1
* ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer2013-06-041-0/+1
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-042-20/+126
* Second part of pr16069Rafael Espindola2013-06-041-4/+9
* Typo: s/caes/cases/ in SimplifyCFGHans Wennborg2013-06-041-1/+1
* Preserve const correctness.Benjamin Kramer2013-06-041-3/+3
* Test commit for user vmedic, to verify commit access. One line of comment is ...Vladimir Medic2013-06-041-1/+1
* Silencing an MSVC warning about mixing bool and unsigned int.Aaron Ballman2013-06-041-1/+1
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