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* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-021-1/+1
* When determining the new index for an insertelement, we may not assume that anNick Lewycky2013-06-011-7/+9
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ...Venkatraman Govindaraju2013-06-011-0/+6
* SimplifyCFG: Fix typo in comment for ComputeSpeculationCostDavid Majnemer2013-06-011-1/+1
* Move getRealLinkageName to a common place and remove all the duplicates of it.Benjamin Kramer2013-06-014-65/+25
* Move object construction into [] so the temporary can be moved.Benjamin Kramer2013-06-011-5/+3
* APInt: Simplify code. No functionality change.Benjamin Kramer2013-06-011-36/+2
* APFloat: Use isDenormal instead of hand-rolled code to check for denormals.Benjamin Kramer2013-06-011-1/+1
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-014-155/+54
* TMP: LEA64_32r fixingTim Northover2013-06-014-54/+155
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-014-32/+45
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-014-30/+79
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-319-39/+40
* Prevent loop-unroll from making assumptions about undefined behavior.Andrew Trick2013-05-311-5/+14
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-314-45/+32
* Const-ify some printing and dumping code for DIEValues.Eric Christopher2013-05-312-13/+13
* Add support for adding the contents of a StringRef to the MD5 hash.Eric Christopher2013-05-311-0/+8
* Convert more unsigned char -> uint8_t.Eric Christopher2013-05-311-1/+1
* Fix comment.Eric Christopher2013-05-311-1/+1
* Move "unsigned char" -> "uint8_t".Eric Christopher2013-05-311-8/+8
* LoopVectorize: Change API call to get the backedge taken countArnold Schwaighofer2013-05-311-3/+3
* Loop Strength Reduce: Scaling factor cost.Quentin Colombet2013-05-313-3/+74
* Rename COFFYaml.h to COFFYAML.h for consistency.Rafael Espindola2013-05-311-1/+1
* Don't allocate temporary string for section data.Rafael Espindola2013-05-311-0/+17
* LoopVectorize: PHIs with only outside users should prevent vectorizationArnold Schwaighofer2013-05-311-13/+30
* NVPTX: Don't even create a regalloc if we're not going to use it.Benjamin Kramer2013-05-311-2/+7
* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-311-6/+45
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-314-29/+42
* Remove useless code from transitioning to new EH schemeKai Nacke2013-05-311-4/+1
* ARM: permit upper-case BE/LE on setend instructionTim Northover2013-05-311-1/+1
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-313-8/+70
* Simplify multiplications by vectors whose elements are powers of 2.Rafael Espindola2013-05-311-16/+48
* ARM: fix VEXT encoding corner caseTim Northover2013-05-311-5/+6
* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-312-9/+27
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-318-66/+307
* [msan] Handle mixed track-origins and keep-going settings (llvm part).Evgeniy Stepanov2013-05-311-4/+6
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-314-32/+45
* Fix ScalarEvolution::ComputeExitLimitFromCond for 'or' conditions.Andrew Trick2013-05-311-32/+54
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-311-2/+16
* Reapply with r182909 with a fix to the calculation of the new indices forNick Lewycky2013-05-312-2/+257
* Remove debug print added in r182949.Ahmed Bougacha2013-05-301-1/+0
* Revert r182937 and r182877.Rafael Espindola2013-05-301-17/+3
* Use the const_cast only where necessary.Bill Wendling2013-05-301-4/+4
* MCObjectSymbolizer: Switch from IntervalMap to sorted vector, following r182625.Ahmed Bougacha2013-05-301-10/+46
* Implement IEEE-754R 2008 nextUp/nextDown functions in the guise of the functi...Michael Gottesman2013-05-301-20/+228
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-305-100/+74
* Fix rematerialization into physical registers.Tim Northover2013-05-301-2/+3
* [NVPTX] Fix case where a sext load of an i1 type may produce anJustin Holewinski2013-05-301-2/+4
* X86: change zext moves to use sub-register infrastructure.Tim Northover2013-05-305-71/+74
* [SystemZ] Enable unaligned accessesRichard Sandiford2013-05-302-0/+11