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* DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0...Benjamin Kramer2013-05-211-1/+2
* Fix indentationRichard Sandiford2013-05-211-9/+9
* Add cmake bits for md5.Eric Christopher2013-05-211-0/+1
* Add an md5 library derived from a public domain implementation for dwarf4Eric Christopher2013-05-211-0/+266
* Dwarf: use a single line table to generate assembly when .loc is used.Manman Ren2013-05-211-3/+14
* Add some additional functions to the list of helper functions forReed Kotler2013-05-211-2/+13
* PR14606: Debug Info for namespace aliases/DW_TAG_imported_moduleDavid Blaikie2013-05-203-11/+44
* The DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase...Bill Wendling2013-05-202-5/+5
* No need to store the TargetMachine variable in this class.Bill Wendling2013-05-201-4/+2
* Remove unused #include.Bill Wendling2013-05-201-1/+0
* Rename LoopSimplify.h to LoopUtils.hHal Finkel2013-05-202-2/+2
* [mips] Add (setne $lhs, 0) instruction selection pattern.Akira Hatanaka2013-05-201-0/+2
* [mips] Trap on integer division by zero.Akira Hatanaka2013-05-204-5/+58
* Remove copied preheader insertion logic from PPCCTRLoopsHal Finkel2013-05-201-85/+3
* Expose InsertPreheaderForLoop from LoopSimplify to other passesHal Finkel2013-05-201-11/+12
* [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a s...Justin Holewinski2013-05-201-9/+7
* [NVPTX] Add programmatic interface to NVVMReflect passJustin Holewinski2013-05-202-3/+24
* Rename PPC MTCTRse to MTCTRloopHal Finkel2013-05-203-7/+7
* Add a PPCCTRLoops verification passHal Finkel2013-05-203-0/+164
* R600: Fix bug detected by GCC warning.Benjamin Kramer2013-05-201-2/+2
* R600/SI: Use a multiclass for MUBUF_Load_HelperTom Stellard2013-05-202-20/+30
* R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructionsTom Stellard2013-05-201-0/+1
* R600/SI: Add pattern for rotrTom Stellard2013-05-201-0/+2
* R600: Swap the legality of rotl and rotrTom Stellard2013-05-207-28/+11
* R600/SI: Add patterns for 64-bit shift operationsTom Stellard2013-05-202-3/+22
* R600/SI: Use the same names for VOP3 operands and encoding fieldsTom Stellard2013-05-202-37/+37
* R600/SI: Make fitsRegClass() operands constTom Stellard2013-05-202-2/+3
* VSTn instructions have a number of encoding constraints which are not impleme...Mihai Popa2013-05-202-21/+72
* Q registers are encoded in fields of the same length as D registers. As Q reg...Mihai Popa2013-05-201-1/+1
* [SystemZ] Add long branch passRichard Sandiford2013-05-2011-34/+399
* [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputsJustin Holewinski2013-05-207-80/+525
* [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need...Justin Holewinski2013-05-201-2/+12
* PR15868 fix.Stepan Dyatkovskiy2013-05-205-11/+69
* Also expand 64-bit bitcasts.Jakob Stoklund Olesen2013-05-201-0/+2
* Implement spill and fill of I64Regs.Jakob Stoklund Olesen2013-05-201-2/+9
* Mark i64 SETCC as expand so it is turned into a SELECT_CC.Jakob Stoklund Olesen2013-05-201-0/+2
* Replace some bit operations with simpler ones. No functionality change.Benjamin Kramer2013-05-193-12/+9
* Don't use %g0 to materialize 0 directly.Jakob Stoklund Olesen2013-05-192-4/+2
* Select i64 values with %icc conditions.Jakob Stoklund Olesen2013-05-191-0/+5
* Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>Bob Wilson2013-05-191-0/+3
* Add floating point selects on %xcc predicates.Jakob Stoklund Olesen2013-05-191-0/+10
* Implement SPselectfcc for i64 operands.Jakob Stoklund Olesen2013-05-192-27/+31
* [Sparc] Rearrange integer registers' allocation order so that register alloca...Venkatraman Govindaraju2013-05-192-10/+23
* Handle i64 FrameIndex nodes in SPARC v9 mode.Jakob Stoklund Olesen2013-05-191-1/+1
* AArch64: make RuntimeDyld relocations idempotentTim Northover2013-05-191-2/+22
* Invalidate instruction cache when setting memory to be executable.Tim Northover2013-05-191-0/+3
* isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.David Majnemer2013-05-181-0/+11
* LoopVectorize: Handle single edge PHIsArnold Schwaighofer2013-05-181-4/+4
* Check InlineAsm clobbers in PPCCTRLoopsHal Finkel2013-05-181-0/+15
* AArch64: add CMake dependency to fix very parallel buildsTim Northover2013-05-181-0/+2