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* Don't use getNextOperandForReg().Jakob Stoklund Olesen2012-08-082-2/+8
| | | | | | | | | This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161542 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use getNextOperandForReg() in RAFast.Jakob Stoklund Olesen2012-08-081-8/+4
| | | | | | That particular optimization was probably premature anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161541 91177308-0d34-0410-b5e6-96231b3b80d8
* Deal with irreducible control flow when building traces.Jakob Stoklund Olesen2012-08-081-17/+22
| | | | | | | | | | | We filter out MachineLoop back-edges during the trace-building PO traversals, but it is possible to have CFG cycles that aren't natural loops, and MachineLoopInfo doesn't include such cycles. Use a standard visited set to detect such CFG cycles, and completely ignore them when picking traces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161532 91177308-0d34-0410-b5e6-96231b3b80d8
* Heed -stress-early-ifcvt.Jakob Stoklund Olesen2012-08-081-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161513 91177308-0d34-0410-b5e6-96231b3b80d8
* Get the MispredictPenalty from MCSchedModel.Jakob Stoklund Olesen2012-08-081-5/+6
| | | | | | Thanks, Andy! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161507 91177308-0d34-0410-b5e6-96231b3b80d8
* Typedefs and indentation fixes from the Andy Zhang/PAX macro argument patch.Rafael Espindola2012-08-081-26/+28
| | | | | | Committing it first as it makes the "real" patch a lot easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161491 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for .pdata and .xdata section attributes on COFF.Anton Korobeynikov2012-08-082-8/+4
| | | | | | | Patch by kai@redstar.de ! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161487 91177308-0d34-0410-b5e6-96231b3b80d8
* Add `.pushsection', `.popsection', and `.previous' directives to Darwin ASM.Bill Wendling2012-08-081-2/+39
| | | | | | | | | | | | | | | | | | | | | There are situations where inline ASM may want to change the section -- for instance, to create a variable in the .data section. However, it cannot do this without (potentially) restoring to the wrong section. E.g.: asm volatile (".section __DATA, __data\n\t" ".globl _fnord\n\t" "_fnord: .quad 1f\n\t" ".text\n\t" "1:" :::); This may be wrong if this is inlined into a function that has a "section" attribute. The user should use `.pushsection' and `.popsection' here instead. The addition of `.previous' is added for completeness. <rdar://problem/12048387> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161477 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-084-9/+9
| | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanup of defaultDefLatency APIAndrew Trick2012-08-081-6/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161470 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-08-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161469 91177308-0d34-0410-b5e6-96231b3b80d8
* isAllocLikeFn is allowed to return true for functions which read memory; makeEli Friedman2012-08-081-2/+9
| | | | | | | | | sure we account for that correctly in DeadStoreElimination. Fixes a regression from r158919. PR13547. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161468 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Fix a quadratic algorithm in MachineBranchProbabilityInfo."Jakob Stoklund Olesen2012-08-082-16/+9
| | | | | | It caused an assertion failure when compiling consumer-typeset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161463 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: enable CSE between CMP and SUBManman Ren2012-08-085-49/+116
| | | | | | | | | | | | | | | We perform the following: 1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering. 2> Modify MachineCSE to correctly handle implicit defs. 3> Convert SUB back to CMP if possible at peephole. Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled by peephole now. rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't scan physreg use-def chains looking for a PIC base.Jakob Stoklund Olesen2012-08-081-10/+4
| | | | | | | | | | We can't rematerialize a PIC base after register allocation anyway, and scanning physreg use-def chains is very expensive in a function with many calls. <rdar://problem/12047515> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161461 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a quadratic algorithm in MachineBranchProbabilityInfo.Jakob Stoklund Olesen2012-08-082-9/+16
| | | | | | | | The getSumForBlock function was quadratic in the number of successors because getSuccWeight would perform a linear search for an already known iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161460 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid recomputing the unique exit blocks and their insert points when doingDan Gohman2012-08-081-11/+26
| | | | | | | | | | multiple scalar promotions on a single loop. This also has the effect of preserving the order of stores sunk out of loops, which is aesthetically pleasing, and it happens to fix the testcase in PR13542, though it doesn't fix the underlying problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161459 91177308-0d34-0410-b5e6-96231b3b80d8
* Skip tied operand pairs that already have the same register.Jakob Stoklund Olesen2012-08-071-10/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161454 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-074-0/+35
| | | | | | | This adds support for TargetIndex operands during isel. The meaning of these (index, offset, flags) operands is entirely defined by the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161453 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a serious typo in InstCombine's optimization of comparisons.Bob Wilson2012-08-071-1/+1
| | | | | | | | | An unsigned value converted to floating-point will always be greater than a negative constant. Unfortunately InstCombine reversed the check so that unsigned values were being optimized to always be greater than all positive floating-point constants. <rdar://problem/12029145> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161452 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cmp lowering is looking past truncate on the condition node. It should onlyEvan Cheng2012-08-071-6/+16
| | | | | | | | | do so when the high bits are known zero. This caused a subtle miscompilation. rdar://12027825 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161451 91177308-0d34-0410-b5e6-96231b3b80d8
* For non-Darwin platforms, we want to generate stack protectors only forBill Wendling2012-08-071-1/+10
| | | | | | | | character arrays. This is in line with what GCC does. <rdar://problem/10529227> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161446 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new kind of MachineOperand: MO_TargetIndex.Jakob Stoklund Olesen2012-08-071-0/+7
| | | | | | | | | | | | A target index operand looks a lot like a constant pool reference, but it is completely target-defined. It contains the 8-bit TargetFlags, a 32-bit index, and a 64-bit offset. It is preserved by all code generator passes. TargetIndex operands can be used to carry target-specific information in cases where immediate operands won't suffice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161441 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable lazy compilation in MCJITAndrew Kaylor2012-08-072-13/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161438 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of typos.Jakob Stoklund Olesen2012-08-072-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161437 91177308-0d34-0410-b5e6-96231b3b80d8
* Add trace accessor methods, implement primitive if-conversion heuristic.Jakob Stoklund Olesen2012-08-073-15/+78
| | | | | | | | Compare the critical paths of the two traces through an if-conversion candidate. If the difference is larger than the branch brediction penalty, reject the if-conversion. If would never pay. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161433 91177308-0d34-0410-b5e6-96231b3b80d8
* The dominance computation already has logic for computing if an edge dominatesRafael Espindola2012-08-071-27/+40
| | | | | | | | | | | | | | | | | | | | | | | | a use or a BB, but it is inline in the handling of the invoke instruction. This patch refactors it so that it can be used in other cases. For example, in define i32 @f(i32 %x) { bb0: %cmp = icmp eq i32 %x, 0 br i1 %cmp, label %bb2, label %bb1 bb1: br label %bb2 bb2: %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ] %foo = add i32 %cond, %x ret i32 %foo } GVN should be able to replace %x with 0 in any use that is dominated by the true edge out of bb0. In the above example the only such use is the one in the phi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161429 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a comment about mftb vs. mfspr on PPC.Hal Finkel2012-08-071-0/+4
| | | | | | Thanks to Alex Rosenberg for the suggestion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161428 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the representation of debug line table in DebugInfo LLVM library,Alexey Samsonov2012-08-073-48/+134
| | | | | | | | | | | | | | and "instruction address -> file/line" lookup. Instead of plain collection of rows, debug line table for compilation unit is now treated as the number of row ranges, describing sequences (series of contiguous machine instructions). The sequences are not always listed in the order of increasing address, so previously used std::lower_bound() sometimes produced wrong results. Now the instruction address lookup consists of two stages: finding the correct sequence, and searching for address in range of rows for this sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161414 91177308-0d34-0410-b5e6-96231b3b80d8
* PR13095: Give an inline cost bonus to functions using byval arguments.Benjamin Kramer2012-08-071-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | We give a bonus for every argument because the argument setup is not needed anymore when the function is inlined. With this patch we interpret byval arguments as a compact representation of many arguments. The byval argument setup is implemented in the backend as an inline memcpy, so to model the cost as accurately as possible we take the number of pointer-sized elements in the byval argument and give a bonus of 2 instructions for every one of those. The bonus is capped at 8 elements, which is the number of stores at which the x86 backend switches from an expanded inline memcpy to a real memcpy. It would be better to use the real memcpy threshold from the backend, but it's not available via TargetData. This change brings the performance of c-ray in line with gcc 4.7. The included test case tries to reproduce the c-ray problem to catch regressions for this benchmark early, its performance is dominated by the inline decision of a specific call. This only has a small impact on most code, more on x86 and arm than on x86_64 due to the way the ABI works. When building LLVM for x86 it gives a small inline cost boost to virtually any function using StringRef or STL allocators, but only a 0.01% increase in overall binary size. The size of gcc compiled by clang actually shrunk by a couple bytes with this patch applied, but not significantly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161413 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR13412, a nasty miscompile due to the interleavedChandler Carruth2012-08-071-11/+17
| | | | | | | | | | | | | | | | | | instsimplify+inline strategy. The crux of the problem is that instsimplify was reasonably relying on an invariant that is true within any single function, but is no longer true mid-inline the way we use it. This invariant is that an argument pointer != a local (alloca) pointer. The fix is really light weight though, and allows instsimplify to be resiliant to these situations: when checking the relation ships to function arguments, ensure that the argumets come from the same function. If they come from different functions, then none of these assumptions hold. All credit to Benjamin Kramer for coming up with this clever solution to the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161410 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a much more conservative strategy for aligning branch targets.Chandler Carruth2012-08-071-15/+49
| | | | | | | | | | | | | Previously, MBP essentially aligned every branch target it could. This bloats code quite a bit, especially non-looping code which has no real reason to prefer aligned branch targets so heavily. As Andy said in review, it's still a bit odd to do this without a real cost model, but this at least has much more plausible heuristics. Fixes PR13265. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161409 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineCSE: Update the heuristics for isProfitableToCSE.Manman Ren2012-08-071-0/+23
| | | | | | | | | | If the result of a common subexpression is used at all uses of the candidate expression, CSE should not increase the live range of the common subexpression. rdar://11393714 and rdar://11819721 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161396 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r161371. Removing the 'const' before Type is a "good thing".Bill Wendling2012-08-071-12/+12
| | | | | | | | | | --- Reverse-merging r161371 into '.': U include/llvm/Target/TargetData.h U lib/Target/TargetData.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161394 91177308-0d34-0410-b5e6-96231b3b80d8
* The define for 64 bit sign extension neglected to Jack Carter2012-08-071-7/+8
| | | | | | | | | | | | | | | | | | | | | initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161377 91177308-0d34-0410-b5e6-96231b3b80d8
* Constify the Type parameter to some methods (which are const anyway).Bill Wendling2012-08-071-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161371 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.Andrew Trick2012-08-071-3/+3
| | | | | | | | | | | This allows codegen passes to query properties like InstrItins->SchedModel->IssueWidth. It also ensure's that computeOperandLatency returns the X86 defaults for loads and "high latency ops". This should have no significant impact on existing schedulers because X86 defaults happen to be the same as global defaults. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161370 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips relocation R_MIPS_64 relocates a 64 bit double word.Jack Carter2012-08-072-0/+4
| | | | | | | | | I hit this in a very large program (spirit.cpp), but have not figured out how to make a small make check test for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161366 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 Jack Carter2012-08-062-14/+10
| | | | | | | | | | | were using a class defined for 32 bit instructions and thus the instruction was for addiu instead of daddiu. This was corrected by adding the instruction opcode as a field in the base class to be filled in by the defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.Jack Carter2012-08-064-2/+30
| | | | | | | | | | | | | | | These 2 relocations gain access to the highest and the second highest 16 bits of a 64 bit object. R_MIPS_HIGHER %higher(A+S) The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. R_MIPS_HIGHEST %highest(A+S) The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161348 91177308-0d34-0410-b5e6-96231b3b80d8
* MFTB on PPC64 should really be encoded using MFSPR.Hal Finkel2012-08-061-2/+2
| | | | | | | | | | | The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the OpenBSD for Bitrig.Eric Christopher2012-08-065-9/+14
| | | | | | Patch by David Hill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161344 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove empty overrides of processFunctionBeforeFrameFinalized().Roman Divacky2012-08-063-10/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161328 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires ↵Craig Topper2012-08-065-55/+187
| | | | | | custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove custom inserter for MWAIT. It doesn't do anything that couldn't be ↵Craig Topper2012-08-052-24/+2
| | | | | | represented in a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161306 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a COPY node instead of an explicit MOVA opcode in the custom insterter ↵Craig Topper2012-08-051-2/+1
| | | | | | for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161305 91177308-0d34-0410-b5e6-96231b3b80d8
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-042-1/+8
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
* Skip impdef regs during eabi save/restore list emission to workaround PR11902Anton Korobeynikov2012-08-041-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161301 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack ↵Anton Korobeynikov2012-08-041-0/+4
| | | | | | | | | | stuff (this corresponds by spilling/reloading regs in DTriple / DQuad reg classes). No testcase, found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161300 91177308-0d34-0410-b5e6-96231b3b80d8
* Add stack spill / reload instructions for DTriple and DQuad register ↵Anton Korobeynikov2012-08-041-3/+43
| | | | | | | | | classes, which were missed for no reason. This fixes PR13377 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
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